MCP37D11-200.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 MCP37D11-200 데이타시트 다운로드

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MCP37231/21-200
MCP37D31/21-200
200 Msps, 16-/14-Bit Low-Power ADC with 8-Channel MUX
Features
• Sample Rates:
- 200 Msps for single-channel mode
- 200 Msps/number of channels used
• SNR with fIN = 15 MHz and -1 dBFS:
- 74.7 dBFS (typical) at 200 Msps
• SFDR with fIN = 15 MHz and -1 dBFS:
- 90 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 490 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 436 mW at 200 Msps, Output Clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 390 mW at 200 Msps
• Power-Saving Modes:
- 144 mW during Standby
- 28 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 VP-P
• Input Channel Bandwidth: 500 MHz
• Channel-to-Channel Crosstalk in Multi-Channel
Mode (Input = 15 MHz, -1 dBFS): >95 dB
• Output Data Format:
- Parallel CMOS, DDR LVDS
- Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
• Serial Peripheral Interface (SPI)
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Fractional Delay Recovery (FDR) for time-
delay corrections in multi-channel operations
(dual-/octal-channel modes)
- Phase, Offset and Gain adjust of individual
channels
- Digital Down-Conversion (DDC) with I/Q or
fS/8 output (MCP37D31/21-200)
- Continuous wave beamforming for octal-
channel mode (MCP37D31/21-200)
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• AutoSync Mode to Synchronize Multiple Devices
to the Same Clock
• Package Options:
- VTLA-124 (9 mm x 9 mm x 0.9 mm)
- TFBGA-121 (8 mm x 8 mm x 1.08 mm)
• No External Reference Decoupling Capacitor
Required for TFBGA Package
• Industrial Temperature Range: -40°C to +85°C
Typical Applications
• Communication Instruments
• Cellular Base Stations
• Radar
• Ultrasound and Sonar Imaging
• Scanners and Low-Power Portable Instruments
• Industrial and Consumer Data Acquisition System
MCP372XX/MCP37DXX Family Comparison(1):
Part Number
Sample Rate
Resolution
Digital
Digital
CW
Decimation(2) Down-Conversion(3) Beamforming(4)
Noise-Shaping
Requantizer(2)
MCP37231-200 200 Msps
16
Yes
No
No
MCP37221-200 200 Msps
14
Yes
No
No
MCP37211-200 200 Msps
12
Yes
No
No
MCP37D31-200 200 Msps
16
Yes
Yes
Yes
MCP37D21-200 200 Msps
14
Yes
Yes
Yes
MCP37D11-200 200 Msps
12
Yes
Yes
Yes
Note 1:
2:
3:
4:
Devices in the same package type are pin-to-pin compatible.
Available in single- and dual-channel mode.
Available in single- and dual-channel mode, and octal-channel mode when CW beamforming is enabled.
Available in octal-channel mode.
No
No
Yes
No
No
Yes
2014-2016 Microchip Technology Inc.
DS20005322D-page 1

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MCP37231/21-200 AND MCP37D31/21-200
Functional Block Diagram
AVDD12
AVDD18
GND
DVDD12
DVDD18
CLK+
CLK-
Clock
Selection
Duty Cycle
Correction
DLL
PLL
AIN0+
AIN0-
AIN7+
AIN7-
VCM
SENSE
VBG
Output Clock Control
Pipelined
ADC
Digital Signal Post-Processing:
- FDR, Decimation
- Phase/Offset/Gain Adj.
- DDC, CW Beamforming
(MCP37D31/21-200)
VREF+
VREF-
Reference
Generator
Output Control:
- CMOS, DDR LVDS
- Serialized LVDS
Internal Registers
DCLK+
DCLK-
WCK
OVR
Q[15:0]
SLAVE
REF1+ REF1- REF0+ REF0- SDIO SCLK CS SYNC
DS20005322D-page 2
2014-2016 Microchip Technology Inc.

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MCP37231/21-200 AND MCP37D31/21-200
Description
The MCP37231/21-200 is Microchip's baseline 16-/14-
bit 200 Msps pipelined ADC family, featuring built-in
high-order digital decimation filters, gain and offset
adjustment per channel and fractional delay recovery.
The MCP37D31/21-200 device family features digital
down-conversion and CW beamforming capability, in
addition to the features offered by the MCP37231/21-
200.
All devices feature harmonic distortion correction and
DAC noise cancellation that enable high-performance
specifications with SNR of 74.7 dBFS (typical), and
SFDR of 90 dBc (typical).
These A/D converters exhibit industry-leading low-
power performance with only 490 mW operation while
using the LVDS interface at 200 Msps. This superior
low-power operation coupled with high dynamic
performance makes these devices ideal for various
high-performance, high-speed data acquisition
systems, including communications equipment, radar
and portable instrumentation.
The output decimation filter option improves SNR
performance up to 93.5 dBFS with the 512x decimation
setting. The digital down-conversion option, in
conjunction with the decimation and quadrature output
options, offers great flexibility in digital communication
system design, including cellular base-stations and
narrow-band communications. Gain, phase and DC
offset can be adjusted independently for each input
channel, allowing for simplified implementation of CW
beamforming and ultrasound Doppler imaging
applications.
These devices can have up to eight differential input
channels through an input MUX. The sampling rate is
up to 200 Msps when a single channel is used, or
25 Msps per channel when all eight input channels are
used.
In dual or octal-channel mode, the Fractional Delay
Recovery (FDR) feature digitally corrects the difference
in sampling instance between different channels, so
that all inputs appear to have been sampled at the
same time.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after 28
clock cycles of data latency. Latency will increase if any
of the digital signal post-processing (DSPP) options are
enabled.
AutoSync mode offers a great design flexibility when
multiple devices are used in applications. It allows
multiple devices to sample input synchronously at the
same clock.
The differential full-scale analog input range is
programmable up to 2.975 VP-P. The ADC output data
can be coded in two's complement or offset binary
representation, with or without the data randomizer
option. The output data is available as full-rate CMOS
or Double-Data-Rate (DDR) LVDS. Additionally, a
serialized LVDS option is also available for the 16-bit
octal-channel mode.
These devices also include various features designed
to maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment
and programmable digital pattern generation. The
device’s operational modes and feature sets are
configured by setting up the user-programmable
registers.
The device is available in Pb-free VTLA-124 and
TFBGA-121 packages. The device operates over the
commercial temperature range of -40°C to +85°C.
Package Types
Bottom View
Dimension: 9 mm x 9 mm x 0.9 mm
(a) VTLA-124 Package.
Bottom View
Dimension: 8 mm x 8 mm x 1.08 mm
Ball Pitch: 0.65 mm
Ball Diameter: 0.4 mm
(b) TFBGA-121 Package.
2014-2016 Microchip Technology Inc.
DS20005322D-page 3

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MCP37231/21-200 AND MCP37D31/21-200
NOTES:
DS20005322D-page 4
2014-2016 Microchip Technology Inc.

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MCP37231/21-200 AND MCP37D31/21-200
1.0 PACKAGE PIN CONFIGURATIONS
AND FUNCTION DESCRIPTIONS
Top View
(Not to Scale)
A68
A1
A2
AIN6+ A3
AIN2+ A4
AIN4+ A5
AIN0+ A6
VCMIN A7
AIN1- A8
AIN7- A9
AIN3- A10
AIN5- A11
A12
A13
A14
A15
NC
A16
NC
A67
AVDD18 GND AVDD12 REF0- REF0+ AVDD12 VBG REF1- REF1+ AVDD12 VCM
A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55
SCLK SDIO
A54 A53
A52
B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42
Note 2
AVDD18 REF0- REF0+
SENSE REF1- REF1+
CS DVDD18
B1 AVDD18
B41
B2 AIN6-
B3 AIN2-
B4 AIN4-
VTLA-124
(9 mm x 9 mm x 0.9 mm)
B40
DVDD12 B39
WCK/OVR+
(OVR) B38
B5 AIN0-
Q15/Q7+ B37
B6 AIN1+
B7 AIN7+
B8 AIN3+
EP
(GND)
Note 3
DVDD18 B36
Q12/Q6- B35
Q10/Q5- B34
B9 AIN5+
Q9/Q4+ B33
B10 Q7/Q3+ B32
B11
AVDD12
B12
DVDD18 B31
Q4/Q2- B30
B13
B14
AVDD12
B15 B16
Note 1
CLK- ADR0 SYNC GND RESET DCLK+ DM2/DM- DVDD18 Q1/Q0+ Q2/Q1- DVDD18
B29
B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28
NC
A51
A50 Note 2
A49
A48
A47
A46
A45
WCK/OVR-
(WCK)
A44 Q14/Q7-
A43 Q13/Q6+
A42 Q11/Q5+
A41 DVDD18
A40 Q8/Q4-
A39 Q6/Q3-
A38 Q5/Q2+
A37
A36
NC
A35
A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34
Note 2
CLK+ AVDD18 SLAVE
DVDD12 CAL DCLK- DM1/DM+ Q0/Q0- DVDD12 Q3/Q1+
Note 2
Note 1: Tie to GND or DVDD18. ADR1 is internally bonded to GND.
2: NC – Not connected pins. These pins can float or be tied to ground.
3: Exposed pad (EP – back pad of the package) is the common ground (GND) for analog and digital
supplies. Connect this pad to a clean ground reference on the PCB.
FIGURE 1-1:
VTLA-124 Package. See Table 1-1 for the pin descriptions and Table 1-3 for active
and inactive ADC output pins for various ADC resolution modes.
2014-2016 Microchip Technology Inc.
DS20005322D-page 5