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FEELING
TECHNOLOGY
FM8PB53B
OTP-Based 8-Bit Microcontroller
Devices Included in this Data Sheet:
FM8PB53B : OTP device
FEATURES
Only 42 single word instructions
All instructions are single cycle except for program branches which are two-cycle
13-bit wide instructions
All OTP area GOTO instruction
All OTP area subroutine CALL instruction
8-bit wide data path
5-level deep hardware stack
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
Pins # I/O #
OTP (Word)
RAM (Byte)
FM8PB53B
14 12
1K
49
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
Two I/O ports IOA and IOB with independent direction control
Soft-ware I/O pull-high/pull-down or open-drain control
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
Wake-up from SLEEP by INT pin or Port B input change
Power saving SLEEP mode
Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
Operating voltage range: 2.0V to 5.5V
- 4MHz: 2.4V to 5.5V
- 8MHz: 2.6V to 5.5V, see 6.1 for more information.
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Web site: http://www.feeling-tech.com.tw
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GENERAL DESCRIPTION
FM8PB53B
The FM8PB53B is a low-cost, high speed, high noise immunity, OTP-based 8-bit CMOS microcontrollers. It
employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program
branches which take two cycles. The easy to use and easy to remember instruction set reduces development
time significantly.
The FM8PB53B consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Oscillator Start-up Timer(OST), Watchdog Timer, OTP, SRAM, tri-state I/O port, I/O pull-high/open-drain/pull-down
control, Power saving SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP
mode, and Code Protection for OTP products. There are three oscillator configurations to choose from, including
the power-saving LF (Low Frequency) oscillator and cost saving RC oscillator.
The FM8PB53B address 1K×13 of program memory.
The FM8PB53B can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
Oscillator
Circuit
Watchdog
Timer
ALU
Interrupt
Control
5-level
STACK
Program
Counter
OT P-R OM
FSR
Instruction
Decoder
8-bit Timer0
Accumulator
DATA BUS
Control
Interrupt
SRAM
PORTA
PORTB
Web site: http://www.feeling-tech.com.tw
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PIN CONNECTION
PDIP, SOP
FM8PB53B
IOA0 1
14 IOA1
IOB7 2
13 IOA2
IOB6 3
12 IOA3
VDD 4 FM8PB53B 11 VSS
IOB5/OSCI 5
10 IOB0/INT
IOB4/OSCO 6
9 IOB1
IOB3/RSTB 7
8 IOB2/T0CKI
PIN DESCRIPTIONS
Name
I/O
Description
IOA0 ~ IOA3
I/O
IOA0 ~ IOA3 as bi-direction I/O pin
Software controlled pull-down
Bi-direction I/O pin with system wake-up function
IOB0/INT
I/O Software controlled pull-high/open-drain/pull-down
External interrupt input
IOB1
I/O
Bi-direction I/O pin with system wake-up function
Software controlled pull-high/open-drain/pull-down
Bi-direction I/O pin with system wake-up function
IOB2/T0CKI I/O Software controlled pull-high/open-drain/pull-down
External clock input to Timer0
Input pin or open-drain output pin with system wake-up function
System clear (RESET) input. Active low RESET to the device. Weak pull-high
IOB3/RSTB I/O always on if configured as RSTB.
Voltage on this pin must not exceed VDD, See IOB3 diagram for detail
description.
Bi-direction I/O pin with system wake-up function (RCOUT optional in IRC/ERIC,
ERC mode)
IOB4/OSCO I/O Software controlled pull-high/open-drain
Oscillator crystal output (HF, XT, LF mode)
Outputs with the instruction cycle rate (RCOUT optional in IRC/ERIC, ERC mode)
Bi-direction I/O pin with system wake-up function (IRC mode)
IOB5/OSCI
I/O
Software controlled pull-high/open-drain
Oscillator crystal input (HF, XT, LF mode)
External clock source input (ERIC, ERC mode)
IOB6 ~ IOB7
I/O
Bi-direction I/O pin with system wake-up function
Software controlled pull-high/open-drain
Vdd - Positive supply
Vss - Ground
Legend: I=input, O=output, I/O=input/output
Web site: http://www.feeling-tech.com.tw
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1.0 MEMORY ORGANIZATION
FM8PB53B
FM8PB53B memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PB53B has a 10-bit Program Counter capable of addressing a 1K×13 program memory space.
The RESET vector for the FM8PB53B is at 3FFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
FM8PB53B supports all OTP area CALL/GOTO instructions without page.
Figure 1.1: Program Memory Map and STACK
PC<9:0>
3FFh
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Reset Vector
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
FM8PB53B
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FM8PB53B
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
Table 1.1: Registers File Map for FM8PB53B
Address
Description
00h INDF
01h TMR0
02h PCL
03h STATUS
04h FSR
05h PORTA
06h PORTB
07h General Purpose Register
08h PCON
09h WUCON
0Ah PCHBUF
0Bh PDCON
0Ch ODCON
0Dh PHCON
0Eh INTEN
0Fh INTFLAG
10h ~ 3Fh
General Purpose Registers
N/A OPTION
05h IOSTA
06h IOSTB
Table 1.2: The Registers Controlled by OPTION or IOST Instructions
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
N/A (w) OPTION
* INTEDG T0CS T0SE PSA PS2 PS1 PS0
05h (w)
IOSTA
Port A I/O Control Register
06h (w)
IOSTB
Port B I/O Control Register
Table 1.3: Operational Registers Map
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
00h (r/w)
INDF
Uses contents of FSR to address data memory (not a physical register)
01h (r/w)
TMR0
8-bit real-time clock/counter
02h (r/w)
PCL
Low order 8 bits of PC
03h (r/w) STATUS
RST
GP1
GP0
T̅̅O̅̅
P̅̅̅D̅
Z
DC
C
04h (r/w)
FSR
*
*
Indirect data memory address pointer
05h (r/w) PORTA
IOA3
IOA2
IOA1
IOA0
06h (r/w) PORTB
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
07h (r/w)
SRAM
General Purpose Register
08h (r/w) PCON WDTE EIS LVDTE
*
*
*
*
*
09h (r/w) WUCON WUB7 WUB6 WUB5 WUB4 WUB3 WUB2 WUB1 WUB0
0Ah (r/w) PCHBUF
-
-
-
-
-
- 2 MSBs Buffer of PC
0Bh (r/w) PDCON
/PDB2 /PDB1 /PDB0 /PDA3 /PDA2 /PDA1 /PDA0
0Ch (r/w) ODCON ODB7 ODB6 ODB5 ODB4
ODB2 ODB1 ODB0
0Dh (r/w) PHCON /PHB7 /PHB6 /PHB5 /PHB4
/PHB2 /PHB1 /PHB0
0Eh (r/w) INTEN
GIE
*
*
*
*
INTIE PBIE
T0IE
0Fh (r/w) INTFLAG
-
-
-
-
-
INTIF PBIF
T0IF
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’,
Web site: http://www.feeling-tech.com.tw
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