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TECHNOLOGY
FM8PE55/E57
EPROM/ROM-Based 8-Bit Microcontroller Series
Devices Included in this Data Sheet:
FM8PE55E/E57E : EPROM devices
FM8PE55/E57 : Mask ROM devices
FEATURES
Only 47 single word instructions
All instructions are single cycle except for program branches which are two-cycle
13-bit wide instructions
All ROM/EPROM area GOTO/FGOTO instruction
All ROM/EPROM area subroutine CALL/FCALL instruction
8-bit wide data path
5-level deep hardware stack
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
Pins # I/O # EPROM/ROM (Word) RAM (Byte)
FM8PE55/E55E 28
20
512
48
FM8PE57/E57E 28
20
2K
96
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
Three I/O ports IOA, IOB and IOC with independent direction control
16 soft-ware control pull-high pins: Port B/Port C
8 soft-ware control pull-down pins:IOA0~A3/IOB0~B3
2 soft-ware control open-drain pins: IOC6/IOC7
One internal interrupt source: Timer0 overflow; One external interrupt source: INT pin
Wake-up from SLEEP by Port B/IOC4/IOC5 input falling
Power saving SLEEP mode
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- XT: Crystal/Resonator Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev1.5 May 21, 2010
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FM8PE55/E57
GENERAL DESCRIPTION
The FM8PE55/E57 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit
CMOS microcontrollers. It employs a RISC architecture with only 47 instructions. All instructions are single cycle
except for program branches which take two cycles. The easy to use and easy to remember instruction set reduces
development time significantly.
The FM8PE55/E57 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer
(PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O
pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,
Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are four oscillator
configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.
The FM8PE55/E55E address 512×13 of program memory, and the FM8PE57/E57E address 2K×13 of program
memory.
The FM8PE55/E57 can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
Oscillator
Circuit
Watchdog
Timer
ALU
Interrupt
Control
5-level
STACK
Program
Counter
EPROM
/ ROM
Timer0
FSR
SRAM
Instruction
Decoder
Accumulator
PORTA
PORTB
PORTC
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PIN CONNECTION
PDIP, SOP
T0CKI 1
28 RSTB
Vdd 2
27 OSCI
NC 3
26 OSCO
Vss 4
25 IOC7
NC 5
24 IOC6
IOA0 6
23 IOC5
IOA1 7 FM8PE55/E55E 22 IOC4
IOA2 8 FM8PE57/E57E 21 IOC3
IOA3 9
20 IOC2
IOB0/INT 10
19 IOC1
IOB1 11
18 IOC0
IOB2 12
17 IOB7
IOB3 13
16 IOB6
IOB4 14
15 IOB5
FM8PE55/E57
SSOP
Vss 1
28 RSTB
T0CKI 2
27 OSCI
Vdd 3
26 OSCO
Vdd 4
25 IOC7
IOA0 5
24 IOC6
IOA1 6
23 IOC5
IOA2 7 FM8PE55/E55E 22 IOC4
IOA3 8 FM8PE57/E57E 21 IOC3
IOB0/INT 9
20 IOC2
IOB1 10
19 IOC1
IOB2 11
18 IOC0
IOB3 12
17 IOB7
IOB4 13
16 IOB6
Vss 14
15 IOB5
PIN DESCRIPTIONS
Name
I/O
Description
IOA0 ~ IOA3
I/O IOA0 ~ IOA3 as bi-direction I/O port
IOB0/INT
I/O Bi-direction I/O pin with system wake-up function / External interrupt input
IOB1 ~ IOB7 I/O Bi-direction I/O port with system wake-up function
IOC0 ~ IOC7 I/O Bi-direction I/O port
T0CKI
I
Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current
consumption
RSTB
I System clear (RESET) input. This pin is an active low RESET to the device.
OSCI
I
X’tal type: Oscillator crystal input
RC type: Clock input of RC oscillator
OSCO
O
X’tal type: Oscillator crystal output.
RC mode: Outputs with the instruction cycle rate
Vdd - Positive supply
Vss - Ground
Legend: I=input, O=output, I/O=input/output
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FM8PE55/E57
1.0 MEMORY ORGANIZATION
FM8PE55/E57 memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PE55/E55E have a 9-bit Program Counter (PC) capable of addressing a 512×13 program memory space.
The FM8PE57/E57E have an 11-bit Program Counter capable of addressing a 2K×13 program memory space.
The RESET vector for the FM8PE55/E55E is at 1FFh. The RESET vector for the FM8PE57/E57E is at 7FFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
FM8PE57/E57E has program memory size greater than 1K words, but the CALL and GOTO instructions only have
a 10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow
CALL and GOTO instructions to address the entire 2K program memory address range for FM8PE57/E57E, there is
another one bit to specify the program memory page. This paging bit comes from the PCHBUF<2> bit. When doing
a CALL or GOTO instruction, the user must ensure that page bit PCHBUF<2> are programmed so that the desired
program memory page is addressed. When one of the return instructions is executed, the entire 11-bit PC is POPed
from the stack. Therefore, manipulation of the PCHBUF <2> is not required for the return instructions.
User can use “PAGE” instruction to change memory page and maintains the program memory page. Otherwise,
user can use “FCALL(far call)/FGOTO(far goto)” instructions to program user's code.
FIGURE 1.1: Program Memory Map and STACK
PC<10:0>
PC<8:0>
7FFh
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Reset Vector
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
1FFh Reset Vector
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
FM8PE55/E55E
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
FM8PE57/E57E
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FM8PE55/E57
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
In FM8PE57/E57E, the data memory is partitioned into four banks. Switching between these banks requires the
RP1 and RP0 bits in the FSR register to be configured for the desired bank. User can use “BANK” instruction to
change the data memory bank.
TABLE 1.1: Registers File Map for FM8PE57/E57E Series
FSR<7:6>
Description
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
00
Bank 0
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCON
WUCON
PCHBUF
PDCON
BPHCON
CPHCON
INTEN
INTFLAG
01
Bank 1
10
Bank 2
11
Bank 3
Memory back to address in Bank 0
10h General
| Purpose
2Fh Registers
N/A OPTION
05h IOSTA
06h IOSTB
07h IOSTC
30h
General
General
General
General
|
Purpose
Purpose
Purpose
Purpose
3Fh
Registers
Registers
Registers
Registers
Rev1.5 May 21, 2010
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