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TOSHIBA
1l:55\T1864J/F1l-10/12/15
SILICON GATE CMOS
PRELIMINARY
65,536 WORD x 18 BIT CMOS STATIC RAM
Description
The TC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits
and operated from a single 3.3V supply. Toshiba's advanced CMOS technology and circuit design enable hJ9!:l speed operation.
The TC55V1864J/FT features low power dissipation when the device is deselected using chip enable (CE), and has an output
enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls.
The TC55V1864J/FT is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and
outputs are LVTTL compatible.
The TC55V1864J/FT is available in a 400mil width, 44-pin plastic SOJ and thin small outline package (forward type) suitable for
high density surface assembly.
Features
• Fast access time
- TC55V1864J/FT -10
- TC55V1864J/FT -12
- TC55V1864J/FT -15
• Low power dissipation
10ns (max.)
12ns (max.)
15ns (max.)
Cycle Time
10
Operation (max.)
- Standby:
1mA (max.)
• Single 3.3V power supply: 3.3V±O.3V
• Fully static operation
• Inputs and outputs LVTTL compatible
• Output buffer control:
OE
• Data byte controls:
LB,UB
• Package
- TC55V1864J: SOJ44-P-400
- TC55V1864FT: TSOP44-P-400
Pin Names
AO - A15
1/01 - 1/018
CE
WE
OE
LB, UB
VDD
GND
NU*
Address Inputs
Data InputS/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power (+3.3V)
Ground
Not Usable (Input)
Pin Connection (Top View)
TCSSV1864J
A4
A3
A2
Al
AO
IT
1/01
1/02
1/03
1/04
Voo
GND
1105
1/06
1/07
1/08
1109
WE
A15
A14
A13
A12
(50J)
A5
A6
A7
OE
US
LB
1/018
11017
1/016
1/015
GND
Voo
1/014
1/013
11012
1/011
11010
NU
A8
A9
Al0
All
A4
A3
A2
Al
AO
CE
1/01
1/02
1/03
1/04
Voo
GND
1/05
1/06
1/07
1/08
1/09
WE
A15
A14
A13
A12
TCS5V1864FT
0
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 2S
21 24
22 23
(T50P)
AS
A6
A7
OE
US
LB
1/018
1/017
1/016
1/015
GND
Voo
1/014
1/013
1/012
1/011
1/010
NU
AS
A9
Al0
All
* The NU pin must be kept electronically open, pulled down to GND, or
less than O.BV. Applying a voltage greater than O.BV to the NU pin is
prohibited.
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
8-137

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TC55V1864J/FT-10/12115
Block Diagram
Static RAM
MEMORY
CELL ARRAY
2S4ix256x 18
(1,179,648)
+-0 VOD
+-0 GND
!~~II!I=l~ ====E::J
1/ t
1/ t
11 t - r I l l l l n n_ _- '
Wl~~~1
m
UI
LJ
t ! o---~--<C>---- CE
Operating Mode
~MODE
CE OE WE Ii UB
1/01 -1/09
1/010 - 1/018 POWER
Read
Write
Output Disable
Standby
LL
Output
Output
1000
L L H H L High Impedance Output
1000
LH
Output
High Impedance 1000
LL
Input
Input
1000
L * L H L High Impedance Input
1000
LH
Input
High Impedance 1000
L H H * * High Impedance High Impedance 1000
L * * H H High Impedance High Impedance 1000
H * * * * High Impedance High Impedance loos
*H or L
Maximum Ratings
SYMBOL
ITEM
RATING
UNIT
Voo Power Supply Voltage
VIN Input Voltage
VI/O InpuVOutput Voltage
Po Power Dissipation
TSOLOER Soldering Temperature • Time
TSTRG Storage Temperature
TOPR Operating Temperature
-0.5 - 4.6
V
-0.5* - 4.6
V
-0.5* - Voo + 0.5** V
1.2 W
260· 10
°C· sec
-65 - 150
°C
-10 - 85
°C
•/** Not yet specified
B-138
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY

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Static RAM
TC55V1864J/FT-10/12115
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Voo Power Supply Voltage
VIH Input High Voltage
VIL Input Low Voltage
*/** Not yet specified
MIN. TYP.
MAX.
UNIT
3.0 3.3
3.6
V
2.0 - Voo + 0.3** V
-0.3* -
0.8 V
=DC Characteristics (Ta 0 - 70°C, Voo =3.3V±0.3V)
SYMBOL
PARAMETER
TEST CONDITION
III
ILO
II(NU)
V OH
VOL
1000
IOOS1
IOOS2
Input Leakage Current (except NU Pin)
Output Leakage Current
Input Current (NU Pin)
Output High Voltage
Output Low Voltage
Operating Current
Standby Current
VIN = 0 - Voo
CE = VIH or WE = VIL or OE = VIH
VOUT= 0 - Voo
VIN = 0 - 0.8V
VIN = 0 - 0.2V
10H = -2mA
10H = -20JlA
10L = 2mA
10L = 20~A
CE = VIL, lOUT = OmA,
Other Inputs = VIHNIL
tcycle = 10ns
tcycle = 12ns
tcycle = 15ns
tcycle = 20ns
tcycle = 30ns
CE = VIH ,
Other Inputs = VIHNIL
CE = Voo - 0.2V
=Other Inputs Voo - 0.2V or 0.2V
--
MIN. TYP. MAX. UNIT
- - ±1 JlA
- - ±1 JlA
-1
-
2.4
Voo - 0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
--
20
±1
-
-
0.4
--
0.2
260
220
200
180
150
20
1
JlA
---
V
mA
--
mA
Capacitance* (Ta =25°C, f =1.0MHz)
SYMBOL
PARAMETER
TEST CONDITION
CIN Input Capacitance
CliO InpuVOutput Capacitance
V IN = GND
VI/O = GND
*This parameter is periodically sampled and is not 100% tested.
MAX.
6
8
UNIT
pF
pF
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
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TC55V1864J/FT-10112115
Static RAM
= =AC Characteristics (Ta 0 - 70°C(1), VDO 3.3V±O.3V)
Read Cycle
SYMBOL
PARAMETER
tRc
tACC
tco
tOE
tBA
tOH
tCOE
tOEE
tBE
tcoo
tO~~
tBo
Read Cycle Time
Address Access Time
CE Access Time
OE Access Time
UB, LB Access Time
Output Data Hold Time from Address Change
Output Enable Time from CE
Output Enable Time from OE
Output Enable Time from UB, LB
Output Disable Time from CE
Output Disable Time from OE
Output Disable Time from UB, LB
TC55V1864J/FT -10 TC55V1864J/FT -12 TC55V1864J/FT -15
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
10 -
12 -
15 -
- 10 -
12 -
15
- 10 - 12 - 15
- 5- 6- 8
- 5-6- 8
3-
3-
3-
3-
3-
3 - ns
1-
1-
1-
1-
1-
1-
- 6- 7- 8
- 6-7- 8
- 6- 7- 8
Write Cycle
SYMBOL
PARAMETER
twc
twp
tew
tBW
tAW
tAs
tWR
tos
tOH
tOEW
tODW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
UB, LB Enable to End of Write
Address Valid to End of Write
Address Setup Time
Write Recovery Time
Data Setup Time
Data Hold Time
Output Enable Time from WE
Output Disable Time from WE
AC Test Conditions
Input Pulse Levels
Input Pulse Rise and Fall Time
Input Timing Measurement Reference Levels
Output Timing Measurement Reference Levels
Output Load
TC55V1864J/FT -10 TC55V1864J/FT -12 TC55V1864J/FT -15
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
10 -
12 -
15 -
7-
8-
9-
9 - 10 - 11 -
9 - 10 - 11 -
9 - 10 - 11 -
0-
0-
0 - ns
0-
0-
0-
6-
7-
8-
0-
1-
0-
1-
0-
1-
- 6- 7- 8
3.0V/0.OV
3ns
1.5V
1.5V
Fig. 1
1I0pin
0 -....- -..
3.3V
I/Opin
. lCL=5pf
12000
(For teol. to... tCOD.
tooo. tOiw and toow)
Figure 1.
8-140
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
PRELIMINARY

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Timing Waveforms
Read Cycle (2)
ADDRESSES
Static RAM
TC55V1864J/FT·10/12115
Dout--------------~----------~
Write Cycle 1 (5) (WE Controlled)
ADDRESSES
Dout
Din
High ,Impedance
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
8-141