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_________________ 680S-Series Microprocessors and Microcomputers
Product Preview
CDP680SG2, CDP680SG2C
TERMINAL ASSIGNMENT
mn
TIfO
'eo",
,',".
''""
'''''''s""""""s ""'"""""""0
""""""""""""""""""""
'00
OSCI
om
TIMER
''''''''""""0"""0
'''''"'"""""".
TOP VIEW
CMOS High-Performance Silicon-Gate
a-Bit Microcomputer
Features:
• Typical full speed operating power
of 12 mWat5 V
• Typical WAIT mode power of 4 mW
• Typical STOP mode power of 5 /JW
• Fully static operation
• 112 bytes of on-chip RAM
• 2106 bytes 01 on-chip ROM
• 32 bidirectionalI/O lines
• High current drive'
• Internal B-bit timer with soltware
programmable 7-bit prescaler
• External timer input
• External and timer interrupts
• Self-check mode
• Master reset and power-on reset
• Single 3 to 6 volt supply
• On-chip oscillator with RC or crystal
mask options
• True bit manipulation
• Addressing modes with indexed
addressing for tables:
The CDP6805G2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers This 8-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer. The fully static design allows operation at frequencies
down to DC, further reducing its already low-power
consumption. It isa low-powerprocessordesigned for low-
end to mid-range applications in the consumer, automotive,
industrial, and communications markets where very low
power consumption constitutes an important factor.
-=-. .
TIMER
RESET NUM IRO
I3 2
Port
B
1/0
lines
PBO
PBI
PB2
PB3
PB4
PB5
PB6
PB7
Port
A
1/0
Lines
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
Port Data
B D"
Reg Reg
Port
A
Reg
Data
Dir
Reg
Accumulator
8A
Index
Register
8X
Condition
Code
Register CC
Stack
6 POinter
S
Program
Counter
High PCH
Program
Counter
8 low PCl
CPU
CPU
Control
AlU
Data
Dir
Reg
Port
C
Reg
Data
Dir
Reg
Port
D
Reg
PCO
PCI Pon
PC2 C
PC3 1/0
PC4 Lines
PC5
PC6
PC7
PDO
PDI
PD2
PD3
PD4
PD5
PD6
PD7
Port
D
1/0
Lines
198x8
Self· Check
ROM
Fig. 1 - CDP6805G2 CMOS microcomputer block diagram.
File Number 1364
------------___________________________________________________ 329

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6805-Serles MicroproCessors and Microcomputers
CDP6805G2, CDP6805G2C
MAXIMUM RATINGS (Voltages Referenced to VSS)
Ratings
Supply Voltage
All Input Voltages Except OSCI
Current Drain Per Pin Excluding VDD and VSS
Operating Temperature Range
CDP6805G2
CDP6805G2C
Storage Temperature Range
Current Drain Total (PD4-PD7 only)
Symbol
VDD
Yin
I
TA
Tstg
IOH
Value
-0.3 to +8
VSS-0.5 to VDD+0.5
10
TL TH
oto +70
-40 to +85
-55 to +150
40
Unit
V
V
mA
°C
°C
mA
THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Plastic
Ceramic
Port
Band C
A. POO·P03
P04·P07
Rl
243 kO
121 kO
3000
R2
4.32 kO
3.1 kO
1.64 kO
ImA)
50
Symbol Value Unit
- 100 -
OJA 50 'C/W
Test POint
This deVice contains Circuitry to protect the
Inputs against damage due to high static
voltages of electnc helds; however. It IS ad-
Vised that normal precautions be taken to
aVOid application of any voltage higher than
maximum rated voltages to thiS high Im-
pedance CirCUIt. For proper operation It IS
recommended that Y,n and Vout be con-
strained to the range Vsss IV In or
Vout) s VOO. Reliability of operation IS
enhanced If unused Inputs except OSC2 and
NU M are tied to an appropriate logiC voltage
level Ie g.• either VSS or VOOI.
VOO=4.5V
-ILoad
A2
50 pF
A1
40
-0
~
C
:l;'
u 3.0
g'"
W
o0.
~
is.
~ 20
Fig. 2 - Equivalent test load.
VOO=6V
Voo=5V
10
01 02 03 0.4 0.5 06 0.7 0.8
Internal Frequency 11/tcyc)
Fig. 3 - Typical operating current VS. internal frequency.
1.0
IMHz)
330 _________________________________________________________________

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6805-Serles Microprocessors and Microcomputers
CDP6805G2, CDP6805G2C
DC ELECTRICAL CHARACTERISTICS (VOO=3 Vdc, Vss=O Vdc, TA=iL to TH, unless otherwise noted)
Output Voltage ILoadS t /JA
Characteristics
Output High Voltage
(ILoad= - 50 /JA) PBO-PB7, PCO-PC7
Symbol
VOL
VOH
VOH
Min
VOO-O 1
1.4
Max
01
-
-
II Load = -0.5 mA)PAO-PA7, POO-P03
IILoad- -2 rnA) P04-P07
Output Low Voltage
II Load = 300 /JA) All Ports
PAO-PA7, PBO-PB7, PCO-PC7, POO-P07
Input High Voltage
Ports PAO-PA7, PBO-PB7, PCO-PC7, POO-P07
TIMER, IRO, RESET
OSCI
Input Low Voltage All Inputs
Total Supply Current (no dc Loads, tcyc=5 /Js)
VOH
VOH
VOL
1.4
1.4
-
03
'{JH. 2.7 VOO
VIH 2.7 VOO
VIH 2.7 VOO
VIL VSS
0.3
Unit
V
V
V
V
V
V
V
V
V
V
RUN (measured during self-check, VIL=O.I V, VIWVOO-O.I V)
WAIT (See Note)
STOP (See Note)
1/ 0 Ports Input Leakage
PAO-PA7, PBO- PB7, PCO-PC7, POO-P07
Input Current
RESET, IRO, TIMER, OSCI
Capacitance
Ports
RESET, IRO, TIMER, OSCI
100 -
100
IJ2J2 -
IlL -
lin -
~ut -
C,n
0.5 rnA
200 /JA
100 I'A
5 I'A
± I I'A
12 pF
8 pF
DC ELECTRICAL CHARACTERISTICS (VOO=5 Vdc ± 10%, VSS=O Vdc TA=TL to TH unless otherwise noted)
Output Voltage ILoad S 1O.I'A
Characteristics
Output High Voltage
=II Load -100 I'AI PBO-PB7, PCO-PC7
Symbol
VOL
VOH
VOH
Min
VOO-O 1
24
Max
01
-
-
Unit
V
V
V
=II Load -2 mAl PAO-PA7, POO-P03
VOH
24
V
IILoad= 8 mAl P04-P07
Output Low Voltage
=II Load 800 I'AI All Ports
PAO-PA7, PBO-PB7, PCO-PC7, POO-P07
Input High Voltage
Ports PAO-PA7, PBO-PB7, PCO-PC7, POO-P07
TIMER, IRO, RESE\ascI
Input Low Voltage All Inputs
Total Supply Current (CL - 50 pF
on Ports, no dc Loads, tcyc= 1 I'sl
RUN Imeasured dUring seit-check,
VIL 02 V, VIH-VOO 0.2 VI
WAIT (See Note)
STOP (See Note)
1/0 Ports Input Leakage
PAD-PA7, PBO- PB7, PCO·PC7, POO-P07
Input Current
RESET, IRO, TIMER, OSCI
Capacitance
Ports
RESET, IRO, TIMER, ascI
VOH
VOL
2.4
-
0.4
VIH Voo-2
VOO
VIH
VOO 08
VOO
VIL VSS 08
100 -
100
!J:llL
IlL -
lin -
Cout
C,n
-
4
1.5
150
± 10
±I
12
8
V
V
V
V
V
rnA
rnA
I'A
I'A
I'A
pF
pF
NOTE: Test cond,tlons for 100 are as follows.
All ports programmed as inputs
VIL = 02 V (PAO-PA7, PSO-PS7, PCO-PC7, POO-P071
VIH = VOO-0.2 V for REm, IRO, TIMER
ascI Input IS a squarewavs from 0.2 V to VOO-O 2 V
OSC2 output load = 20 pF (walt 100 IS affected linearly by the
OS C2 eapaella neeI
331
III

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6a05-Series Microprocessors and Microcomputers
CDP6805G2, CDP6805G2C
TABLE 1 - CONTROL TIMING
(VDD=5 Vdc ± 10%, VSs=O, TA=TL to THo losc=4 MHz)
Characteristics
Crystal OSCillator Startup Time (Figure 51
Stop Recovery Startup Time (Crystal Oscillatorl (Figure 61
Timer Pulse Width (Figure 41
Reset Pulse Width (Figure 51
Timer Penod (Figure 41
Interrupt Pulse Width low (Figure 151
Interrupt Pulse Penod tFigure 151
OSCI Pulse Width
Cycle Time
Frequency 01 Operation
Crystal
External Clock
Symbol
Min
Max
U~it
toxOV
-
100 nis
IIlCH
-
100 ms
lTH, tTL
0,5
-
tcyc
tRl 1,5
-
tCl!c
-lTlTl
1
-
tcyc
tlLlH 1 - tcyc
*tlLll
- tc~c
tOH, tOl
100
-
ns
tcyc 1000
-
n,j
losc
tosc
-
DC
4 MHz
Mrjz
"The minimum penod tlLll should not be less than the number 01 tcyc cycles It takes to execute the Interrupt service routines plus 20 tcyc cycles
External
Clock
(
Timer)
Pin 37
Fig. 4 - Timer relationships.
~r----------------------------------------------------
VOD
~;}Z1ZZZZZZ/l777727ZZZIZZZZZZl27ZZZ77ZI7/7ZZlZZZZZZ7ZZ7Z7ZZ/
osc,**
:. -I.I
'OXOV
I
I
·11920 tc,c
I I i'c'c1
rLS
INTERNAL
*ADDRESS
BUS
INTERNAL
*DATA
BUS
' t ¥RESET
* INTERNAL TIMING SIGNAL AND BUS INFORMATION NOT AVAILABLE EXTERNALLY
**OSCI LINE IS NOT MEANT TO REPRESENT FREQUENCY,
IT IS ONLY USED TO REPRESENT TIME,
92CM-38J03
Fig. 5 - Power-on RESET and RESET.
332 _________________________________________________________________

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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP6805G2, CDP6805G2C
(;:SE(NS0ITI~VE~~:~*~~W////:0:I W&.:J~ffi
ONLY
~ t LCH
1920 teye
RESET
--------------------------------
~2* ------------------------~
.. INTERNAL TIMING SIGNALS NOT AVAILABLE EXTERNALLY,
* * REPRESENTS THE INTERNAL GATING OF THE CSCI INPUT PIN.
92CS-38101
Fig. 6 - Stop recovery and power-on RESET.
FUNCTIONAL PIN DESCRIPTION
VDD and VSS
Power IS supplied to the MCU uSing these two pins. VDD
IS power and VSS IS ground.
iRO (MASKABLE INTERRUPT REQUEST)
IRQ is mask option selectable With the choice of Interrupt
sensitivity being both level- and negative-edge or negatlve-
edge only.The MCU completes the current Instruction
before It responds to the request. If IRQ IS low and the Inter-
rupt mask bit II bit) In the condition code register IS clear, the
MCU beginS an Interrupt sequence at the end of the current
instruction.
If the mask option IS selected to Include level sensitivity,
then the IRQ Input requires an external resistor to VDD for
"wire-OR" operation. See the Interrupt section for more
detail
RESET
The RESET Input IS not required for start-up but can be
used to reset the MCU's Internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed deSCription
TIMER
The TIMER Input may be used as an external clock for the
on-chip lImer Refer to Timer section for a detailed deSCrip-
tion.
NUM - NON-USER MODE
This pin IS Intended for use In self-check only User ap-
plications should connect this pin to ground through a 10 kO
resistor
OSC1,OSC2
The CDP6805G2 can be configured to accept either a
crystal input or an RC network. Additionally, the internal
clocks can be derived by either a divide-by-two or divide-
by-four of the external frequency (fOSC). Both of these
options are mask selectable.
RC - If the RC oscillator option IS selected, then a resistor
IS connected to the oscillator pms as shown In Figure 71b)
The relationship between Rand fosc IS shown In Figure 8.
CRYSTAL - The circuit shown In Figure 71a) IS recom-
mended when uSing a crystal. The Internal oscillator IS
deSigned to Interface With an AT-cut parallel resonant quartz
crystal resonator In the frequency range specified for fosc In
the electrical characteristics table. USing an external CMOS
oscillator IS suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the Input pins to minimize
output distortion and start-up stabilization time Crystal fre-
quency limits are also affected by VDD. Refer to Control
Timing Characteristics for limits. See Table 1
EXTERNAL CLOCK - An external clock should be ap-
plied to the OSC1 Input With the OSC2 Input not connected,
as shown In Figure 71e). An external clock may be used With
either the RC or crystal oscillator mask option. toxOV or
t)LCH do not apply when uSing an external clock input.
III
________________________________________________________________________________ 333