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__________________________ CMOS Peripherals
Advance Information
TERMINAL ASSIGNMENT
MOT
OSCI
24 Voo
23 sew
OSC2
ADO
22 PS
21 CKour"
ADI
AD2
AD3
AD4
AD5
7
8
9
20 C KFS
19 TAo
18 'R"E"SE'T
17 os
16 STBY
AD6
10
'5 R/W
"AD7
VSS
'2
cs'4 AS
'3
92C5-42690
24-Lead Dual-In-Llne Package
CDP6818A
CMOS Real-Time Clock Plus RAM
Features:
• Low-power, high-speed CMOS
• Internal time base and oscillator
• Counts seconds, minutes, and hours of the day
• Counts days of the week, date, month, and year
• 3 V to 6 V operation
• Time base input options: 4.194304 MHz, 1.048576 MHz, or 32.768 kHz
• Time base oscillator for parallel resonant crystals
• 40 to 200 pW typical operating power at low frequency time base
• 4.0 to 20 mW typical operating power at high frequency time base
The COP6818A Real-Time Clock plus RAM is a peripheral
device which includes the unique MOTEL concept for use
with various microprocessors, microcomputers, and larger
computers. This part combines three unique features: a
complete time-of-day clock with alarm and one hundred
year calendar, a programmable periodic interrupt and
square-wave generator, and 50 bytes of low-power static
RAM. The COP6818A uses high-speed CMOS technology
to interface with 1 MHz processor buses, while consuming
very little power.
The Real-Time Clock plus RAM has two distinct uses. First,
it is designed as a battery powered CMOS part (in an
otherwise NMOS/TTL system) including all the common
battery backed-up functions such as RAM, time, and
calendar. Secondly, the COP6818A may be used with a
CMOS microprocessor to relieve the software of the
timekeeping workload and to extend the available RAM of
an MPU such as the C0P6805E2.
T£RMINAL ASSIGNMENT
c ;t
>C
o
u>
u>
..
4 3 2 1 28 27 26
PIN'~ADO
AD.
AD2
25 CKOUT
24 CKFS
23 IRQ
AD3
22 RESET
AD4
TOPVIEW
21 OS
AD5
'0
20 ST BY
"N/C
'9
,2 13 14 '5 16 17 18
R/ii
.C
"
z~
...
C
"
!ll~
u>
"
~
Z
92CS-42691
28-Lead Plastic Chip-Carrier Package
(Q Suffix)
• Binary or BCD representation of time, calendar, and
alarm
• 12- or 24-hour clock with AM and PM in 12-hour mode
• Daylight savings time option
• Automatic end of month recognition
• Automatic leap year compensation
• Microprocessor bus compatible
• Selectable between Motorola and competitor bus timing
• Multiplexed bus for pin efficiency
• Interfaced with software as 64 RAM locations
• 14 bytes of clock and control registers
• 50 bytes of general purpose RAM
• Status bit indicates data integrity
• Bus compatible interrupt Signals (IRQ)
• Three interrupts are separately software maskable and
testable
Time-of-day alarm, Once-per-second to
Once-per-day
Periodic rates from 30.5 ps to 500 ms
End-of-clock update cycle
• Programmable square-wave output signal
• Clock output may be used as microprocessor clock input
at time base frequency +1 or +4
lEI
The COP6818A is supplied in a 24-lead dual-in-line plastic
package (E suffix). in a 24-lead dual-in-line side-brazed
ceramic package (0 suffix) and in a 28-lead plastic chip
carrier package (Q suffix).
File Number 2041
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CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP6818A
CKOUT
CKFS
USC I
OSC2
VDD-
Vss-
Bus
Interface
Clock!
Calendar
Update
BCD'
Binary
Irlcrement
sow
Registers A, B, C, D
14 Bytesl
Clock, Alarm,
Calendar RAM
! 10 Bvtesl
User RAM
150 Bvtes!
Fig, 1 - Block diagram,
92C$-42692
MAXIMUM RATINGS (Voltages referenced to Vss)
SUPPLY VOLTAGE, Voo "",","""""",',',""""""""""""''''''''''''''''''''''',',''',''',,,.,'''''' ,{),3 to +8,0 V
ALL INPUT VOLTAGE, V,N " " " " " " " " " " " ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 'V•• ,{),5 to Voo +0,5 V
CURRENT DRAIN PER PIN EXCLUDING Voo and V••, I " " " " " " " " " " " " " " ' " ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' , , : , ' ' ' ' ' ' ' ' ' ' ' ' ' ,10 rnA
OPERATING TEMPERATURE RANGE, TA = Te to TH
CDP6818A "","""',",,',","",',""""",""""'",'''''','''''''''''''''''''''''',',''''''',,''''''''''',,0 to 70'C
CDP6818AC"""""""""",,,,,,,,,,,.,.,,,,,,,,,,,,,.,,,.,,,,,,,,,,,,,,,.,,,,,, ... ,,.,, .. , .. ,,, .. ,,.,,,,,,.,, .-40 to 85'C
STORAGE TEMPERATURE RANGE, T.", ... " . , , , " .... , " . " .. " .. , , " , .. , , , , , , . , , .. , . , " .. , , , ... " .. , , , " .. " .. , '" -55 to +150'C
THERMAL CHARACTERISTICS
THERMAL RESISTANCE, IJJA
Plastic (E Suffix) ... , , , " " " " " " " " " " " " " " ' " " .... '" .. ," " .. "''''''',.".", .. ''''',.,''" ... " .. ,,, .. ,'.,, 120'C/W
Ceramic (D Suffix) .. " ,. """"" "" ,.," .. , .. , ... ," " .... " .... ".,,,.",, .. ,,''''''' .. ,, .. ,, .... ,,,',, .. ,,,,.,,,, .. 50'C/W
Chip-Carrier (Q Suffix)' "" ,.," "'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' " .. """ .. " .. ",,. 8O'C/w
, Printed-circuit board mount: 57 mm x 57 mm minimum area x 1,6 mm thick G10 epoxy glass, or equivalent.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electrical fields;
however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum
rated voltages to this high-impedance circuit. For proper
operation it is recommended that V'N and VOUT be
constrained to the range Vss :S (V'N or VOUT) :S Voe.
Reliability of operation is enhanced if unused inputs are tied
to an appropriate logic voltage level (e.g., eitherVss orVee).
580 _____________________________________________________________

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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP6818A
DC ELECTRICAL CHARACTERISTICS (Voo =3 Vdc, v•• =0 Vdc, T. =TL to TH UnlelS Otherwise Noted)
CHARACTERISTIC
LIMITS
MIN.
MAX.
UNITS
Frequency 01 Operation
Output Voltage
IL••• < 10JJA
loec 32.768 32.768 kHz
VOL -
VOH Voo-O.l
0.1
-
V
100 - Bus Idle
1003
CKOUT =I..c, CL =15 pF; saw Disabled, STBY =0.2 V; CL (OSC2) =10 pF
I..c =32.768 kHz
-
50 pA
100 - auiescent
I..c =DC' OSCl =DC; All Other Inputs =Voo-0.2 V; No Clock
-10D<
50 pA
Output High Voltage
ilL••• =-0.25 rnA All Outputs)
VOH 2.7
-
V
Output Low Voltage
(ILO•• =0.25 rnA All Outputs)
-VOL 0.3 V
Input High Voltage
V,H
STBY, ADO-AD7, OS, AS, RIW, CS
2.1 Voo
RESET,CKFS, PS, OSCl
2.5 Voo
V
MOT
Voo Voo
Input Low Voltage
V,L
STBY, ADO-AD7, OS, AS, R/W, CS, CKFS, PS, RESET, OSCl
MOT
Vss 0.5
Vss Vss
V
Input Current
AS, OS, R/W
MOT, OSCl CE STBY RESET, CKFS, PS
lin
-- ±10 pA
±1
Three-State Leakage
IRa ADO-AD7
hSL
-
±10 JJA
DC ELECTRICAL CHARACTERISTICS (Voo =5 Vdc ± 10%, Vss =0 Vdc; TA =TL to TH Unless Otherwise Noted)
CHARACTERISTIC
LIMITS
MIN.
MAX,
UNITS
Frequency 01 Operation
Output Voltage
IL... < 10 JJA
foac 32.768 4194.304 kHz
VOL -
0.1
VOH Voo-O.l
-
V
100 - Bus Idle (External Clock)
CKOUT =I..c, CL =15 pF; saw Disabled, STBY =0.2 V; CL (OSC2) =10 pF
loac =4.194304 MHz
1001
looc =1.048516 MHz
1002
loao =32.768 kHz
1003
-
-
-
3 rnA
800 pA
50 JJA
100 - auiescent
looc =DC; OSCl =DC; All Other Inputs =Voo-0.2 V; No Clock
100.
-
50 pA
Output High Voltage
(ILO•• =-1.6 rnA, ADO-AD7, CKOUT)
(I L... =-1.0 rnA, SaW)
VOH
4.1
-
V
Output Low Voltage
(ILO•• =1.5 rnA, ADO-AD7, CKOUT)
(ILo•• =1.0 rnA, IRa and SaW)
VOL
-
0.4 V
Input High Voltage
V,H
STBY, CFKS, ADO-AD7, OS, AS, R/W, CS, PS
Voo-2.0
Voo
RESET
OSCl
Voo-0.8
Voo-LO
Voo
Voo
V
MOT
Voo Voo
Input Low Voltage
cs.CKFS, PS, RESET, STBY, ADO-AD7, OS, AS, R/W,
OSCl
MOT
V,L
Vs. 0.8
Vss Vss
V
Input Current
AS, OS, R/W
MOT,OSCl CE, STBY, RESET, CKFS PS
I'n
--
±10
±1
pA
Three-State Leakage
hSL
IRa ADO-AD7
- ±10 p}.
- - - - - -____________________________________________________ 581

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CMOS Perlpherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP6818A
BUS TIMING
~-
IDENT.
NO.
CHARACTERISTIC
Voo = 3.0 V
50 pF LOAD
MIN.
MAX.
Voo = 5.0V ± 10%
1 TTL. 130 pF LOAD
UNITS
MIN.
MAX.
1
2
3
4
8
13
14
15
18
21
24
25
26
27
28
30
31
32
....2L
GycleTime
Pulse Width. DS/E Low or R'iSiwR Hioh
Pulse Width. DS/E High or RD/WR Low
Input Rise and Fall Time
R/W Hold Time
RiWSetup Time Before DS/E
ChiP. Select Setup Time Before OS. WR. or RD
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid Time to AS/ALE Fall
Muxed Address Hold Time
Delav Time DS/E to AS/ALE Rise
Pulse Width. AS/ALE Hioh
Delay Time. AS/ALE to DS/E Rise
Peripheral Output Data Delay Time from
DS/E or AD
Peripheral Data Setup Time
STBY Setup Time Before AS/ALE Rise
STBY Hold Time After AS/ALE Fall
te,e
PWEL
PWEH
t, tf
tRWH
tRWS
tcs
tCH
tOHR
tOHW
tASL
tAHL
tASO
PWASH
IASEO
tOOR
tosw
tass
tSSH
5000
1000
1500
-
10
200
200
10
10
100
200
100
500
600
500
1300
1500
20
100
-
-
-
100
-
-
-
-
1000
-
-
-
-
-
-
-
-
-
-
953
300
325
-
10
80
25
0
10
0
50
20
50
135
60
20
200
20
50
dc ns
- ns
- ns
30 ns
- ns
- ns
- ns
- ns
100 ns
- ns
- ns
- ns
- ns
- ns
- ns
240 ns
- ns
- ns
- ns
NOTE: Designations E. ALE. RD. and WR Refer to signals from alternative microprocessor signals.
VHIGH
AS !\ vLOW
rt0~--:::;:
4
-+ ~0
... ®DS -, ®
2
~ -~ 1
I ry.
-- -0
I->- .-'-0)
~
I
cr
.-.-.- ~
~ ~f,@
~
~
.r-
\\\ \ \ \ \ \1\
~=~ --=- 15
jllill
\\1\\\\
'3"
-®--
m
vxxv®t:-r-- f-.~
ADO·
AD?
WRITE
if
\
lX
6 ....-.0
®-~- 0
111
~. r-e
ADO-
AD?
READ
c--.
Note VHIGH=VDD~20V. VLOW=08V. forVDD=50V ±10% for outputs only
aVHIGH=2 V. VLOW=O 5 V for VDD=3 0 V for outputs only .
9208-42693
582 _______________________Fi_g._2_- _CD_P_68_18_A_b_us_ti_m_ing_. __________________________

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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP6818A
ALE (Address Latch Enablel
lAS Pin I
RD IRead Output Enablel
IDS P,nl
WR (Write Enable)
IR/W Pin I
ES (Chip Selectl
ADO·AD7
(Address/ Data 8usl
Fig. 3 - Bus read timing competitor multiplexed bus.
ALE IAddress Latch Enablel
lAS P,nl ------.;;r-
AD IRead Output Enablel
IDS P,nl
WR (Write Enable)
IR/W P,nl
92CS-42694
CS (Chip Selectl
..~---~H--(33)--+--- ...1
-<1ADOAD7
IAddress/Data 8usl ____________
Write Data
Valid
Note VHIGH = VDD - 20 V. VLOW= 08 V. for VDD= 50 V ± 10% for outputs only
VHIGH=20 V. VLOW=O 5 V, for VDD=3 0 V for outputs only
92CS-42695
Fig. 4 - Bus write timing competitor multiplexed bus.
__________________________________________________________ 583