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Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MWS5101A
A3
A2
AI
AO 4
A5 5
A6
07
V55
01 I
8
9
001 -10
Dr2
II
22
21
20
19
18
17
16
15
14
13
12
TOP VIEW
VDD
A4
R/W
CSf
o0
CS2
004
Dr4
003
DB
002
9ZCS-29976RI
TERMINAL ASSIGNMENT
256-Word by 4-Bit LSI Static
Random-Access Memory
Features:
• Industry standard Pinout
TTL compatible
• Very low operating current-B mA
at Voo = 5 V and cycle time = 1 iJS
Output-Disable for common I/O systems
3-state data output for bus-oriented
• Two Chip-Select Inputs-simple
systems
memory expansion
Separate data inputs and outputs
• Memory retention for standby battery
voltage of 2 V min.
The RCA-MWS51 01 A IS a 256-word by 4-blt static random-
access memory designed for use in memory systems where
high speed, very low operating current, and simplicity In
use are desirable It has separate data inputs and outputs
and utilizes a single power supply of 4 to 6 5 volts.
Two Chip-Select Inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems. The Output Disable input allows these RAM's to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
Independent of the Chip-Select Input condition. The output
assumes a high-impedance state when the Output Disable
is at high level or when the chip is deselected by CSI and/or
CS2
For applications requiring CMOS compatibility over wider
operating voltage and temperature ranges, the mechanical
and functional equivalent RCA-CDPI822 static RAM may
be used
The MWS5101A types are supplied in 22-lead hermetic
dual-in-line, side-brazed ceramic packages (0 suffix). in
22-lead dual-in-line plastic packages (E suffix), and in chip
form (H suffix).
OPERATIONAL MODES
INPUTS
MODE
READ
WRITE
WRITE
STANDBY
STANDBY
OUTPUT DISABLE
Chip Select 1
CS1
a
a
a
1
X
X
Chip Select 2
CS2
1
1
1
X
a
X
Output Disable
00
a
a
1
X
X
1
Logic 1 = High
aLogic = Low
X = Don't Care
Read/Write
R/W
1
a
a
X
X
X
OUTPUT
Read
Data In
High Impedance
High Impedance
High Impedance
High Impedance
File Number 1207
692 ______________________________________________________________

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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
MWS5101A
OPERATING CONDITIONS at TA = Full Package·Temperature Range
For maximum reliability, operating conditions should be selected so that
operation IS always within the following ranges'
LIMITS
CHARACTERISTIC
ALL TYPES
UNITS
Min. Max.
DC Operating·Voltage Range
Input Voltage Range
4
VSS
6.5
VDD
V
MAXIMUM RATINGS, Absolute·Maxlmum Values:
DC SUPPLY·VOLTAGE RANGE (Voo)
(All voltage referenced to V•• terminal) ........................................... -o.S to -7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................-o.S to Voo + O.S V
DC INPUT CURRENT, ANY ONE INPUT ................................................ ± 10 mA
POWER DISSIPATION PER PACKAGE (Po)'
For TA= -40 to +60° C (PACKAGE TYPE E) .......................................... SOO mW
For TA = +60 to +8So C (PACKAGE TYPE E) ........... Derate Linearly at 12 mW/o C to 200 mW
For TA = -S5 to +100°C (PACKAGE TYPE D), ........................................ SOO mW
For TA = +100 to +125°C (PACKAGE TYPE D) ........ Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE·TEMPERATURE RANGE (All Package Types) ......•.....•• 100 mW
OPERATING·TEMPERATURE RANGE (TA).
PACKAGE TYPE D ............................................................000S to +12SoC
PACKAGE TYPE E .............................................................-40 to +8SoC
STORAGE TEMPERATURE RANGE (T...) ............................................as to +lS0°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 Inch (1 59 ± 0.79 mm) from case for 10 s max..•................. +26SoC
STATIC ELECTRICAL CHARACTERISTICS at TA=O to 70°C, VDD =5 V
TEST
.IMITS
CHARACTERISTIC
CONDITIONS
Vo VIN
(V) (V)
MWS5101AD
MWS5101AE
Min. Typ. Max.
UNITS
Quiescent Device
Current, 100
L2Tvoes -
L3Types -
0, 5 -
0, 5 -
25
100
50
200
,..A
Output Voltage:
Low·Level,
HiQh·Level,
Input Low Voltage,
Input High Voltage,
VnL
VOH
VIL
VIH
-
-
-
-
0, 5 -
0, 5 4.9
--
- 2.2
° 0.1
5-
- 0.65
--
V
Output Low (Sink)
Current,
Output High (Source)
Current,
Input Current,
0.4
IOL
0,5
2
4.6 0, 5 -1
IOH
liN -
0,5 -
4-
-2 -
rnA
- ±5
3·State Output Leakage
Current,
L2Types
lOUT
L3Types
Operating Current,
1001#
Input Capacitance,
CIN
Output Capacitance,
COUT
0, 5
0, 5
-
-
-
0, 5
0, 5
0,5
-
-
-
-
-
-
-
- ±5 ,..A
- ±5
4 8 rnA
5 7.5 pF
10 15
="Typical values are for TA 2S·C and nominal VDD.
=#Outputs open-circuited; cycle time 1 "s.
____________________________________________________________ 893

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Random-Acce.. Memorl•• (RAM.) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MWS5101A
= =DYNAMIC ELECTRICAL CHARACTERISTICS at TA 0 to 70 ·C, VDD 5 V ± 5%,
tr,tf = 20 ns, CL = 50 pF and 1 TTL Load
LIMITS
CHARACTERISTIC
MWS5101AD, MWS5101AE
-L2 TYDeS I L3 Types
Mln.t Typ. Max. Mint Typ.- Max.
Read Cycle Times (Fig. 1)
Read Cycle
- -tRC 250
- 350 -
Access from Address ' tAA -
150 250 -
200 350
UNITS
-Output Valid from
Chip·Select 1 tOOA1
150 250 -
200 350
-Output Valid from
Chlp·Select 2 tOOA2
150 250 -
200 350
-Output Valid from
Output Oisable tOOA3
- 110 -
- 150 ns
Output Hold from
20
Chip·Select 1 tOOH1
-
-
20 -
-
Output Hold from
Chip·Select 2
tOOH2
20
-
-
20 -
-
Output Hold from
Output Olsable
tOOH3
20
-
-
20 - -
trime required by a limit device to allow for the indicated function.
"Typical values are for TA = 25'C and nominal VOO.
AO - A7
~I
1 - - - - - 'RC------I
CHIP SELECT 2
OUTPUT DISABLE
READ/WRi'TE
DATA ouT
_
_
~~HI~GH~----~~~O~.T;.~OV~ALUID T~-/
HIGH
IMPEDANCE
IMPEDANCE
Fig. 1 - Read cycle tlmmg waveforms
92CM- 30244R4
894 _________________________________________________________

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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
MWS5101A
= =DYNAMIC ELECTRICAL CHARACTERISTICS at TA 0 to 70 "C, VDD 5 V ± 5%,
tr,t, = 20 ns, CL = 50 pF and 1 TTL Load
LIMITS
CHARACTERISTIC
MWS5101AD, MWS5101AE
L2 Types
L3 Types
Min.t Typ.- Max. Mint Typ'- Max.
Write Cycle Times (Fig. 2)
Write Cycle
Address Setup
Write Recovery
Write Width
Input Data
Setup Time
twc
tAS
tWR
tWRW
300
110
40
150
tDS 150
-
-
-
-
-
- 400 -
- 150 -
- 50 -
- 200 -
- 200 -
-
-
-
-
-
Data In Hold
tDH
Chip·Select 1 Setup tCS1S
Chip·Select 2 Setup tCS2S
Cfilp·Select 1 Hold tCS1H
Chip·Select 2 Hold tCS2H
40
110
110
0
0
-
-
-
-
-
- 50 -
- 150 -
- 150 -
- 0-
- 0-
-
-
-
-
-
Output Disable
Setup
110 -
tODS
- 150 -
-
UNITS
ns
hime required by a limit device to allow for the indicated function.
"TYPical values are for TA=25·C and nominal VOO.
AD-A7
CHIP-SELECT r
CHIP-SELECT 2
OUTPUT DISABLE
011- 014
READ/ WRITE
-------~ 'we
~DON'TCARE
'* toos IS REQUIRED FOR COMMON I/O
OPERATION ONLY,FOR SEPARATE I/O
OPERATIONS. OUTPUT DISABLE IS DON'T CARE
92CM- 30B04R4
Fig Wflte cycle IImmg waveforms
________________________________________________________________ 695

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Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MWS5101A
DATA RETENTION CHARACTERISTICS at TA = 0 to 70" C; See Fig. 3.
CHARACTERISTIC
Minimum Data
Retention Voltage,
Data Retention
Quiescent
Current, 100
VOR
L2Types
L3Types
Chip Deselect to Data
Retention Time,
~OR
Recovery to Normal
Qperation Time,
~
VOO to VOR Rise and
Fall Time
tr,tf
TEST
CONDITIONS
VDR
(V)
VDD
(V)
--
2
-
-
-5
-5
25
LIMITS
All Types
UNITS
Min. Typ. Max.
- 1.5 2 V
-
-
2
5
10
50
,..A
600 - -
ns
600 - -
1 - - ,..s
= r·TYPlcal values are for TA 25 ·C.
DATA RETENTION
MODE
V-"D,,-D_ _":!I..
O~V~D O~D ~'r'CDR
VDR
'Re
eS2
ViH\; I
VIL~
I fViH
¥ V1L 92CS-30e05RI
Fig. 3 - Low Voo data retention tlmmg waveforms
!
I
WRITE
ADDRESS
DECODER
:!.
I
READ
ADDRESS
DECODER
Voo
92CS -272 56R2
Fig. 4 - Memory cell configuration
696 _____________________________________________________________