The .uPD8255 and .uPD8255A-5 Programmable Peripheral Interfaces (PPI) are designed
for use in 8080A/8085A microprocessor systems_ Peripheral equipment can be effectively
and efficiently interfaced to the 8080A/8085A data and control busses with the.uPD8255
and .uPD8255A-5_ The .uPD8255 and .uPD8255A-5are functionally configured to be
programmed by system software to avoid external logic for peripheral interfaces_
Data Bus Buffer
The 3-state, bidirectional, eight bit Data Bus Buffer (DO-D71 of the .uPD8255 and
.uPD8255A-5 can be directly interfaced to the processor's system Data Bus (DO-D7)-
The Data Bus Buffer is controlled by execution of IN and OUT instructions by the
processor. Control Words and Status information are also transmitted via the Data Bus
Read/Write and Control Logic
This block manages all of the internal and external transfers of Data, Control and
Status. Through this block, the processor Address and Control busses can control the
Chip Select, CS, pin 6
A Logic Low, VI L, on this input enables the .uPD8255 and .uPD8255A-5 for com-
munication with the 8080A/8085A.
Read, RD, pin 5
A Logic Low, VIL on this input enables the .uPD8255 and pPD8255A-5 to send Data
or Status to the processor via the Data Bus Buffer.
Write, WR, pin 36
A Logic Low, VIL, on th is input enables the Data Bus Buffer to receive Data or Con-
trol Words from the processor.
Port Select 0, AO, pin 9
Port Select 1, A1, pin 8
These two inputs are used in conjunction with CS, RD, and WR to control the selec-
tion of one of three ports on the Control Word Register. AD and A 1 are usually
connected to AD and Al of the processor Address Bus.
Reset, pin 35
A Logic High, VIH, on this input clears the Control Register and sets ports A, B, and
C to the input mode. The input latches in ports A, B, and C are not cleared.
Group I and Group II Controls
Through an OUT instruction in System S.oftware from the processor, a control word
is transmitted to the .uPD8255 and .uPD8255A-5. Information such as "MODE,"
"Bit SET," and "Bit RESET" is used to initialize the functional configuration of each
Each qroup (I and II) accepts "commands" from the Read/Write Control Logic and
"control words" from the internal data bus and in turn controls its associated I/O
Group I - Port A and upper Port C (PC7-PC4)
Group II - Port B and lower Port C (PC3-PCO)
While the Control Word Register can be written into, the contents cannot be read back
to the processor.
Ports A, B, and C
The three 8-bit I/O ports (A, B, and CI in the .uPD8255 and .uPD8255A-5 can all be
configured to meet a wide variety of functional requirements through system software.
The effectiveness and flexibility of the .uPD8255 and .uPD8255A-5 is further
enhanced by special features unique to each of the ports.
Port A = An 8-bit data output latch/buffer and data input latch.
Port B = An 8-bit data input/output latch/buffer and an 8-bit data input buffer.
Port C = An 8-bit output latch/buffer and a data input buffer (input not latched).
Port C may be divided into two independent 4-bit control and status ports for use with
Ports A and B.