UPD8255.pdf 데이터시트 (총 7 페이지) - 파일 다운로드 UPD8255 데이타시트 다운로드

No Preview Available !

NEe Microcomputers, Inc.
NE'C
fLPD8255
fLPD8255A·5
PROGRAMMABLE PERIPHERAL INTERFACES
D ESCR I PTI ON
The IlPD8255 and IlPD8255A-5 are general purpose programmable INPUT/OUTPUT
devices designed for use with the 8080A/8085A microprocessors. Twenty-four (24)
I/O lines may be programmed in two groups of twelve (group I and group II) and used
in three modes of operation. In the Basic mode, (MODE 0), each group of twelve I/O
pins may be programmed in sets of 4 to be iniJut or output. In the Strobed mode,
(MODE 1), each group may be programmed to have 8 lines of input or output. Three
of the remaining four pins in each group are used for handshaking strobes and interrupt
control signals. The Bidirectional Bus mode, (MODE 2), uses the 8 lines of Port A for
a bidirectional bus, and five lines from Port C for bus control signals. The IlPD8255
and IlPD8255A-5 are packaged in 40 pin plastic dual-in-line packages.
F EATU RES
Fully Compatible with the 8080A/8085 Microprocessor Families
• All Inputs and Outputs TTL Compatible
• 24 Programmable I/O Pins
• Direct Bit SET/RESET Eases Control Application Interfaces
• 8 - 2 mA Darlington Drive Outputs for Printers and Displays (IlPD8255)
• 8 - 4 mA Darlington Drive Outputs for Printers and Displays (IlPD8255A-5)
• LSI Drastically Reduces System Package Count
• Standard 40 Pin Dual-In-Line Plastic and Ceramic Packages
PIN CONFIGURATION
PA3
PA2
PAl
PAo
RD
cs
GND
Al
AO
PC7
pC6
PC5
PC4
PCo
PCl
PC2
PC3
PBo
PBl
PB2
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10
I l PD
8255/
31
11 8255A-5 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
PA4
PA5
PA6
PA7
WR
RESET
Do
Dl
D2
D3
D4
D5
D6
D7
Vcc
PB7
PB6
PB5
PB4
PB3
PIN NAMES
D7- DO
RESET
es
RD
WR
AO. A,
PA7,PAO
PB7-PBO
pe7-pea
Vee
GND
Data Bus {SI-Dlrectlonal}
Reset Input
Chip Select
Read Input
Write Input
Port Address
Port A (Bit}
Port 8 (Bltl
Port C (Bit)
+5 Volts
o Volts
II
Rev/2
609

No Preview Available !

fL PD8255/8255A·5
General
The .uPD8255 and .uPD8255A-5 Programmable Peripheral Interfaces (PPI) are designed
for use in 8080A/8085A microprocessor systems_ Peripheral equipment can be effectively
and efficiently interfaced to the 8080A/8085A data and control busses with the.uPD8255
and .uPD8255A-5_ The .uPD8255 and .uPD8255A-5are functionally configured to be
programmed by system software to avoid external logic for peripheral interfaces_
FUNCTIONAL DESCRIPTION
Data Bus Buffer
The 3-state, bidirectional, eight bit Data Bus Buffer (DO-D71 of the .uPD8255 and
.uPD8255A-5 can be directly interfaced to the processor's system Data Bus (DO-D7)-
The Data Bus Buffer is controlled by execution of IN and OUT instructions by the
processor. Control Words and Status information are also transmitted via the Data Bus
Buffer.
Read/Write and Control Logic
This block manages all of the internal and external transfers of Data, Control and
Status. Through this block, the processor Address and Control busses can control the
peripheral interfaces.
Chip Select, CS, pin 6
A Logic Low, VI L, on this input enables the .uPD8255 and .uPD8255A-5 for com-
munication with the 8080A/8085A.
Read, RD, pin 5
A Logic Low, VIL on this input enables the .uPD8255 and pPD8255A-5 to send Data
or Status to the processor via the Data Bus Buffer.
Write, WR, pin 36
A Logic Low, VIL, on th is input enables the Data Bus Buffer to receive Data or Con-
trol Words from the processor.
Port Select 0, AO, pin 9
Port Select 1, A1, pin 8
These two inputs are used in conjunction with CS, RD, and WR to control the selec-
tion of one of three ports on the Control Word Register. AD and A 1 are usually
connected to AD and Al of the processor Address Bus.
Reset, pin 35
A Logic High, VIH, on this input clears the Control Register and sets ports A, B, and
C to the input mode. The input latches in ports A, B, and C are not cleared.
Group I and Group II Controls
Through an OUT instruction in System S.oftware from the processor, a control word
is transmitted to the .uPD8255 and .uPD8255A-5. Information such as "MODE,"
"Bit SET," and "Bit RESET" is used to initialize the functional configuration of each
I/O port.
Each qroup (I and II) accepts "commands" from the Read/Write Control Logic and
"control words" from the internal data bus and in turn controls its associated I/O
ports.
Group I - Port A and upper Port C (PC7-PC4)
Group II - Port B and lower Port C (PC3-PCO)
While the Control Word Register can be written into, the contents cannot be read back
to the processor.
--
Ports A, B, and C
The three 8-bit I/O ports (A, B, and CI in the .uPD8255 and .uPD8255A-5 can all be
configured to meet a wide variety of functional requirements through system software.
The effectiveness and flexibility of the .uPD8255 and .uPD8255A-5 is further
enhanced by special features unique to each of the ports.
Port A = An 8-bit data output latch/buffer and data input latch.
Port B = An 8-bit data input/output latch/buffer and an 8-bit data input buffer.
Port C = An 8-bit output latch/buffer and a data input buffer (input not latched).
Port C may be divided into two independent 4-bit control and status ports for use with
Ports A and B.
610

No Preview Available !

BLOCK DIAGRAM
I _ _ _ ' "~OWER \ - - - ,r,v
SUPPllH
fL PD8255/8255A·5
'"PC ~C.
WAITE
CONTROL
LOGIC
a _ _ _ _J
ABSOLUTE MAXIMUM
RATINGS'
Operating Temperature
Storage Temperature ..
All Output Voltages CD .
All Input Voltages CD
Supply Voltages CD ...
Note: CD With respect to VSS
o°c to +70°C
-65°C to +125°C
-0.5 to +7 Volts
-0.5 to +7 Volts
-0.5 to +7 Volts
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specificatIOn IS not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTERISTICS
CAPACITANCE
Ta =o°c to +70°C;Vcc =+5V 10 1O%;VSS =ov
PARAMETER
SYMBOL
LIMITS
/JPD8255
,uPD8255A 5
MIN TVP MAX MIN TVP MAX
UNIT
TEST
CONDITIONS
~u I Low Voltage
In~ut High Voltage
Output Low Voltage
Output High Voltage
Darlington Drive Current
V,L
V,H
VOL
VOH
IOH(1
VSS-O.5
2
2.4
1
0.8 -0.5
Vee 2
04
24
2 4 ~1
0.8
Vee
045
V
v
V
V
~'0
3
~4 mA VOH 1 5V, REXT 750H
Power Supply Current
Input Leakage Current
Input Leakage Current
Output Leakage Current
Output Leakage Current
lee
lLIH
ILiL
ILOH
ILOL
40 120
10
~ 10
10
~10
120 mA Vee '5V, Output Open
10 MA V,N Vee
~1O ,A V,N o 4V
±10 MA VOUT - Vee; CS 20V
~1O MA VOUT - 0 4V. CS 20V
Notes: G)
@
Q)
Any set of eight 38) outputs from e,ther Pon A, 8, or C can source 2 mA ,nlO 1 5V for ",PQ8255. or 4 rnA 11110
1,5V tor ..PD8255A-5
For ..PD8255 IOL 1 7 mA
For .. PD8255A-5 IOL 25 mA for 08 Port. I 7 mA tor Peripheral Porl~
For pPD8255: IOH "" - 100 pA for DB Port: 50}Js for Peripheral Ports.
For pPD8255A-5: IOH 0; -400 pA for dB Port: - 200 ps for Peripheral Ports
Ta = 25°C: VCC = VSS = OV
PARAMETER
Input Capacitance
1/0 Capacitance
SYMBOL
CIN
CliO
LIMITS
MIN TYP MAX UNIT
10 pF
20 pF
TEST CONDITIONS
fc=lMHz
Unmeasured pins
returned to VSS
611

No Preview Available !

,.,. PD8255/8255A·5
T. -Ifc to+7O"c; vee" +!iV:t 5'JI,; vss" ov
.....L..ITS
A·I
PARAMETER
SYMBOL MIN MAX MIN MAX UNIT
TEST
CONDITIONS
.EAD
Address Stll~. Befor. ~
Addr_ Stable Aftn READ
IRQDPuIMWldttI
0.. V.lld From ~D
'"'AR
'RA
,..'RR <OS
300
'RD
0.11 FIOIt After ~
wmrnTime "'I_n iilAD! .,d/or
Adcha St8t:11, Beton WRITE
AddrwI Stllble After WRITE
I wmT'f Put.. WIdth
0.. Valid ToWRI1 (Leo)
0.. Valid After WRITE
'OF
'RV
-'AW
'VIA
'OW
two
,,0
10
.'"
WAITE
'"
20
400
10
3.
10
"'"
20
300
100
30
200
100
8255:Cl.-l00pF
8266A·5: CL .. 150 pF
M CL-1OQpF
M CL-16pF
a>
WR" OTo 0u1(lUt
OlMER TIMING
'VI. 500
,'"
8255: Cl .. 60 pF
8266.A·6: CL .. 150 pF
hrlph'" Datlla.tOf1llm
hrlphera! 0.111 Att. 1m
ACK PuI.. WIchh
. ~PuI.. Widlh
m"',0.111 Beton T.E. Of
Per. DIta Aft., T.E. Of STB
&K-OToOutpUl
'JQ:'R' .. 0 To OutpUt Float
-""-IT.o.,--.
xeR'''OToOBF.'
m"OToI8F·'
RD.' ToIBF-O
_"'1?-OToINTA-O
STI·' To INTA·'
ACK .. 1 To INTR .. 1
'IR
'HR
'AK
"'.'ST
"'H
'AD
'KO
'WOO
tAOB
ISIB
tRIB
"'IT
"IT
I"IT
,.,
,,.,500 '00
500
'0
150 180
400 '00
30.
20
300
4'"
450
360
4"
400
400
'50
20
'5O
350
300
300
400
300
350
8255: CL" 50 pF
8265A·5: CL -1&OpF
82$5{~L·50PF
CL-15pF
82&&: CL .. 60 pF
8266A·5: Cl .. , &0 pF
lIFt .. 0 To INTH .. 0
twiT
850 860
<DNotes: Period of Reset pulse must be at least 50 j.£S during or after power on. Subsequent Reset
pulse can be 500 ns min.
AC CHARACTERISTICS
INPUT FROM PERiPHERAL"
CS. AI. AO ===)j......:'AA==+====4'R=A =~===
WR ______...r-'ww-..,~--...,.--
DO 'WD
D1::::::::~~~::::::::+=:)::::::::
OUTPUT TO PERIPHERAL
_'W~
BASIC OUTPUT - ",P08255
WR-------~==~'W:W:=~r_-----
~ 07::::::::::::~::~~l:OW:t:'W:Dx::::::::
OUTPUT TO PERIPHERAl.
_'w~
BASIC OUTPUT - PP08256A-5
612
TIMING WAVEFORMS
MOOED

No Preview Available !

TIMING WAVEFORMS
(CaNT.)
MODE 1
WR-----·,J
OBF ------+-+--+-......
INTR - - - - - - + -........dl
twiT
ACR-------+------~-~I
OUTPUT TO PERIPHERAL
fL PD825518255A·5
STB FROM PERIPHERAL
I B F - - - -_ _"'I
INTR---------4-~
__R5--------~-~~~I~ jf::::::t----
INPUT FROM
PER IPHERAL
MODE 2
WRITE
DATA FROM ~PD8080A TO ~PD8255 AND ~PD8255A
INTR
ACK FROM PERIPHERAL
STB FROM PERIPHERAL
IBF -------.....,
PERIPHERAL _ _ _ _ _ _ ~=;"';'==H_l
BUS
IRIB
R6------~-----~~--~
DATA FROM
PERIPHERAL TO ~PD8255
AND ~PD8255A-5
READ DATA FROM
~PD8255 AND ~FD8255A-5
TO ~PD8080A
CD WRNote:'
Any sequence where
occurs before ACK and STB occurs before Ri5. is permissible.
IINTR = IBF· MASK· STB· RD + OBF - MASK· ACK - WR)
o When the jJPD8255A~5 is set to Mode 1 or 2, OBF is reset 10 be high (logic 1).
613