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Data Sheet
Quad, 10-Bit nanoDAC®
with 2 ppm/°C Reference, SPI Interface
AD5317R
FEATURES
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5317R, a member of the nanoDAC® family, is a low
power, quad, 10-bit buffered voltage output DAC. The device
includes a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The device operates from a single
2.7 V to 5.5 V supply, is guaranteed monotonic by design, and
exhibits less than 0.1% FSR gain error and 1.5 mV offset error
performance. The device is available in a 3 mm × 3 mm LFCSP
and a TSSOP package.
The AD5317R also incorporates a power-on reset circuit and a
RSTSEL pin that ensures that the DAC outputs power up to
zero scale or midscale and remain at that level until a valid write
takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 µA at 3 V while in power-down mode.
The AD5317R employs a versatile SPI interface that operates at
clock rates up to 50 MHz and contains a VLOGIC pin intended for
1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCLK
SYNC
SDIN
SDO
AD5317R
2.5V
REFERENCE
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
POWER-ON
RESET
GAIN
×1/×2
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
LDAC RESET
RSTSEL
Figure 1.
GAIN
Table 1. Related Devices
Interface
Reference
SPI Internal
External
I2C Internal
External
12-Bit
AD5684R
AD5684
AD5694R
AD5694
10-Bit
AD53171
AD5316R
AD5316
1 The AD5317 and AD5317R are not pin-to-pin or software compatible.
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
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Last Content Update: 02/23/2017
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DOCUMENTATION
Data Sheet
AD5317R: Quad, 10-Bit nanoDAC® with 2 ppm/°C
Reference, SPI Interface Data Sheet
REFERENCE MATERIALS
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DESIGN RESOURCES
AD5317R Material Declaration
PCN-PDN Information
Quality And Reliability
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AD5317R
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Daisy-Chain and Readback Timing Characteristics................ 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Digital-to-Analog Converter .................................................... 19
Transfer Function ....................................................................... 19
DAC Architecture....................................................................... 19
Serial Interface ............................................................................ 20
Standalone Operation ................................................................ 21
REVISION HISTORY
2/14—Rev. 0 to Rev. A
Change to Table 2 ..............................................................................3
Change to Table 7 ............................................................................10
Deleted Figure 10, Renumbered Sequentially .............................11
Deleted Long-Term Temperature Drift Section and
Figure 50 ...........................................................................................25
7/12—Revision 0: Initial Version
Data Sheet
Write and Update Commands.................................................. 21
Daisy-Chain Operation ............................................................. 21
Readback Operation .................................................................. 22
Power-Down Operation ............................................................ 22
Load DAC (Hardware LDAC Pin) ........................................... 23
LDAC Mask Register ................................................................. 23
Hardware Reset (RESET) .......................................................... 24
Reset Select Pin (RSTSEL) ........................................................ 24
Internal Reference Setup ........................................................... 25
Solder Heat Reflow..................................................................... 25
Thermal Hysteresis .................................................................... 25
Applications Information .............................................................. 26
Microprocessor Interfacing....................................................... 26
AD5317R to ADSP-BF531 Interface ....................................... 26
AD5317R to SPORT Interface .................................................. 26
Layout Guidelines....................................................................... 26
Galvanically Isolated Interface ................................................. 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. A | Page 2 of 28

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Data Sheet
AD5317R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
Min
10
Offset Error Drift2
Gain Temperature Coefficient2
DC Power Supply Rejection Ratio2
DC Crosstalk2
OUTPUT CHARACTERISTICS2
Output Voltage Range
Capacitive Load Stability
Resistive Load3
Load Regulation
0
0
1
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
REFERENCE OUTPUT
Output Voltage6
Reference TC7, 8
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
Load Regulation, Sourcing2
Load Regulation, Sinking2
Output Current Load Capability2
Line Regulation2
Thermal Hysteresis2
2.4975
Typ Max
±0.12
0.4
+0.1
+0.01
±0.02
±0.01
±1
±1
0.15
±2
±3
±2
±0.5
±0.5
1.5
±1.5
±0.1
±0.1
±0.1
±0.2
VREF
2 × VREF
2
10
80
80
40
25
2.5
2.5025
25
0.04
12
240
20
40
±5
100
125
25
Unit Test Conditions/Comments
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
ppm
mV/V
µV
µV/mA
µV
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
External reference; gain = 2; TSSOP
Internal reference; gain = 1; TSSOP
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
Due to single channel, full-scale output change
Due to load current change
Due to power-down (per channel)
V
V
nF
nF
µV/mA
µV/mA
mA
Ω
µs
Gain = 1
Gain = 2, see Figure 28
RL = ∞
RL = 1 kΩ
5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT
+30 mA
3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT
+20 mA
See Figure 28
Coming out of power-down mode; VDD = 5 V
V
ppm/°C
Ω
µV p-p
nV/√Hz
µV/mA
µV/mA
mA
µV/V
ppm
ppm
At ambient
See the Terminology section
0.1 Hz to 10 Hz
At ambient; f = 10 kHz, CL = 10 nF
At ambient
At ambient
VDD ≥ 3 V
At ambient
First cycle
Additional cycles
Rev. A | Page 3 of 28

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AD5317R
Data Sheet
Parameter
LOGIC INPUTS2
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)2
Output Low Voltage, VOL
Output High Voltage, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
IDD
Normal Mode9
All Power-Down Modes10
Min
Typ Max
Unit
0.7 × VLOGIC
2
±2
0.3 × VLOGIC
µA
V
V
pF
VLOGIC − 0.4
4
0.4
V
V
pF
Test Conditions/Comments
Per pin
ISINK = 200 μA
ISOURCE = 200 μA
1.8
2.7
VREF + 1.5
5.5
3
5.5
5.5
0.59 0.7
1.1 1.3
14
6
V
µA
V Gain = 1
V Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
mA Internal reference off
mA Internal reference on, at full scale
µA −40°C to +85°C
µA −40°C to +105°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.
2 Guaranteed by design and characterization; not production tested.
3 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 28).
6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Terminology section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
8 Reference temperature coefficient calculated as per the box method. See the Terminology section for more information.
9 Interface inactive. All DACs active. DAC outputs unloaded.
10 All DACs powered down.
Rev. A | Page 4 of 28