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Data Sheet
32-Channel, 3 V/5 V, Single-Supply,
12-Bit, denseDAC
AD5383
FEATURES
Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
featuring data readback)
I2C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical microelectro-mechanical systems (MEMS)
Control systems
Instrumentation
DVDD (×3)
DGND (×3)
FUNCTIONAL BLOCK DIAGRAM
AVDD (×4)
AGND (×4) DAC GND (×4)
REFGND
REFOUT/REFIN SIGNAL GND (×4)
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
DB11/(DIN/SDA)
DB10/(SCLK/SCL)
DB9/(SPI/I2C)
DB8
DB0
A4
A0
REG 0
REG 1
RESET
BUSY
CLR
MON_IN1
MON_IN2
MON_IN3
MON_IN4
AD5383
INTERFACE
CONTROL
LOGIC
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
POWER-ON
RESET
VOUT0………VOUT31
36-TO-1
MUX
12 INPUT 12
REG 0
12 m REG 0
12 c REG 0
12 INPUT 12
REG 1
12 m REG 1
12 c REG 1
12 INPUT 12
REG 6
12 m REG 6
12 c REG 6
12 INPUT 12
REG 7
12 m REG 7
12 c REG 7
×4
1.25V/2.5V
REFERENCE
12
DAC 12
REG 0
DAC 0
12
DAC 12
REG 1
DAC 1
12
DAC 12
REG 6
DAC 6
12
DAC 12
REG 7
DAC 7
R
R
R
R
R
R
R
R
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT31
MON_OUT
Figure 1.
LDAC
Rev. D
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AD5383* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
Application Notes
An-1228: 32 Channels of Programmable Voltage with
Excellent Temperature Drift Performance Using the
AD5383 DAC
AN-1229: AD5383 Channel Monitor Function
AN-214: Ground Rules for High Speed Circuits
Data Sheet
AD5383: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit,
denseDAC Data Sheet
Product Highlight
Extending the denseDAC™ Multichannel D/As
SOFTWARE AND SYSTEMS REQUIREMENTS
AD5380 IIO Multi-Channel DAC Linux Driver
REFERENCE MATERIALS
Solutions Bulletins & Brochures
Digital to Analog Converters ICs Solutions Bulletin
Technical Articles
Software Calibration Reduces D/A Converter Offset and
Gain Errors
DESIGN RESOURCES
AD5383 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD5383 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD5383
TABLE OF CONTENTS
Features .............................................................................................. 1
Integrated Functions ........................................................................ 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
AD5383-5 Specifications ............................................................. 5
AD5383-3 Specifications ............................................................. 7
AC Characteristics........................................................................ 8
Timing Characteristics..................................................................... 9
Serial Interface Timing ................................................................ 9
I2C Serial Interface Timing........................................................ 11
Parallel Interface Timing ........................................................... 12
Absolute Maximum Ratings.......................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Terminology .................................................................................... 18
Typical Performance Characteristics ........................................... 19
Functional Description .................................................................. 22
DAC Architecture—General..................................................... 22
Data Decoding ............................................................................ 22
On-Chip Special Function Registers (SFR) ............................ 23
SFR Commands .......................................................................... 23
Data Sheet
Hardware Functions....................................................................... 26
Reset Function ............................................................................ 26
Asynchronous Clear Function.................................................. 26
BUSY and LDAC Functions...................................................... 26
FIFO Operation in Parallel Mode ............................................ 26
Power-On Reset.......................................................................... 26
Power-Down ............................................................................... 26
Interfaces.......................................................................................... 27
DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 27
I2C Serial Interface ..................................................................... 29
Parallel Interface ......................................................................... 31
Microprocessor Interfacing....................................................... 32
Applications Information .............................................................. 34
Power Supply Decoupling ......................................................... 34
Power Supply Sequencing ......................................................... 34
Typical Configuration Circuit .................................................. 35
Channel Monitor Function ....................................................... 36
Toggle Mode Function............................................................... 36
Thermal Monitor Function....................................................... 36
Optical Attenuators .................................................................... 37
Utilizing the FIFO ...................................................................... 38
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 39
Rev. D | Page 2 of 40

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Data Sheet
REVISION HISTORY
5/14—Rev. C to Rev. D
Deleted ADSP-2103 ...................................................... Throughout
Changed ADSP-2101 to ADSP-BF527 ....................... Throughout
Deleted Table 1; Renumbered Sequentially ...................................3
Changes to General Description Section .......................................4
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................7
Changes to Table 4 ............................................................................9
Changes to Table 6 ..........................................................................12
Changes to Soft Reset Section .......................................................23
Changes to Reset Function Section ..............................................26
Changes to Figure 38 ......................................................................33
Added Power Supply Sequencing Section, Table 18, Figure 39,
and Figure 40; Renumbered Sequentially ....................................34
Added Figure 41 and Figure 42 .....................................................35
10/12—Rev. B to Rev. C
Changes to Product Title and Features Section ............................1
Changes to General Description Section and Table 1; Deleted
Table 2, Renumbered Sequentially..................................................3
AD5383
Changes to Table 3 ............................................................................4
Changes to Table 4 ............................................................................6
Changes to Table 5 ............................................................................7
Changes to Table 6 ............................................................................8
Changes to Table 9 ..........................................................................13
Changes to Figure 10, Figure 11, and Figure 14..........................18
Changes to Figure 16, Figure 17, Figure 18, and Figure 20 .......19
4/10—Rev. A to Rev. B
Changes to Table 18 ........................................................................24
Updated Outline Dimensions........................................................37
Changes to Ordering Guide...........................................................37
3/05—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................3
Changes to Table 3 ............................................................................6
Change to Table 5..............................................................................7
Change to Table 18..........................................................................24
5/04—Revision 0: Initial Version
Rev. D | Page 3 of 40

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AD5383
GENERAL DESCRIPTION
The AD5383 is a complete, single-supply, 32-channel, 12-bit
denseDAC® available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5383 includes a programmable internal 1.25 V/2.5 V,
10 ppm/°C reference; an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring; and an output amplifier boost mode
that allows optimization of the amplifier slew rate. The AD5383
features
Double-buffered parallel interface with a 20 ns WR
pulse width.
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial
interface with interface speeds in excess of 30 MHz.
I2C-compatible interface that supports a 400 kHz data
transfer rate.
Data Sheet
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated independently
or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust register
that allows the user to fully calibrate any DAC channel. With
boost off, power consumption is typically 0.25 mA/channel.
Rev. D | Page 4 of 40