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Data Sheet
8-Bit, 210 MSPS TxDAC® D/A Converter
AD9748
FEATURES
High performance member of pin-compatible
TxDAC product family
Linearity
0.1 LSB DNL
0.1 LSB INL
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.20 V reference
CMOS-compatible digital interface
32-lead LFCSP
Edge-triggered latches
Fast settling: 11 ns to 0.1% full-scale
GENERAL DESCRIPTION
The AD97481 is an 8-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path of
communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based on
performance, resolution, and cost. The AD9748 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.
The AD9748’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.
APPLICATIONS
Communications
Direct digital synthesis (DSS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
0.1µF
RSET 3.3V
CLK+
CLK–
3.3V
1.2V REF
REFIO
FS ADJ
150pF
DVDD
DCOM
SEGMENTED
SWITCHES
AVDD ACOM
CURRENT AD9748
SOURCE
ARRAY
LSB
SWITCHES
IOUTA
IOUTB
CLKVDD
CLKCOM
LATCHES
MODE
CMODE
DIGITAL DATA INPUTS (DB7–DB0)
SLEEP
Figure 1.
Edge-triggered input latches and a 1.2 V temperature-
compensated band gap reference have been integrated to
provide a complete monolithic DAC solution. The digital inputs
support 3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. 32-lead LFCSP.
2. The AD9748 is the 8-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
3. Differential or single-ended clock input (LVPECL or
CMOS), supports 210 MSPS conversion rate.
4. Data input supports twos complement or straight binary
data coding.
5. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
6. On-chip voltage reference: The AD9748 includes a 1.2 V
temperature-compensated band gap voltage reference.
1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
Rev. B
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AD9748* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
AD9748 Evaluation Board
REFERENCE MATERIALS
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
Digital to Analog Converters ICs Solutions Bulletin
DOCUMENTATION
Application Notes
AN-137: A Digitally Programmable Gain and Attenuation
Amplifier Design
AN-302: Exploit Digital Advantages in an SSB Receiver
AN-320A: CMOS Multiplying DACs and Op Amps Combine
to Build Programmable Gain Amplifier, Part 1
AN-642: Coupling a Single-Ended Clock Source to the
Differential Clock Input of Third-Generation TxDAC® and
TxDAC+® Products
AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
AD9748: 8-Bit, 210 MSPS TxDAC D/A Converter Data Sheet
TOOLS AND SIMULATIONS
AD9748 IBIS Model
DESIGN RESOURCES
AD9748 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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TECHNICAL SUPPORT
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AD9748
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Functional Description .................................................................. 11
Reference Operation .................................................................. 11
REVISION HISTORY
3/13—Rev. A to Rev. B
Changed CP-32-2 to CP-32-7 ...........................................Universal
Changes to Figure 3 and Table 5..................................................... 7
Changes to Ordering Guide .......................................................... 24
12/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to General Description and Product Highlights .......... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 4............................................................................ 6
Inserted Figure 7; Renumbered Sequentially................................ 9
Changes to Figure 8 and Figure 9................................................... 9
Data Sheet
Reference Control Amplifier .................................................... 11
DAC Transfer Function ............................................................. 12
Analog Outputs .......................................................................... 12
Digital Inputs .............................................................................. 13
Clock Input.................................................................................. 13
DAC Timing................................................................................ 14
Power Dissipation....................................................................... 14
Applying the AD9748 ................................................................ 15
Differential Coupling Using a Transformer............................... 15
Differential Coupling Using an Op Amp................................ 16
Single-Ended, Unbuffered Voltage Output............................. 16
Single-Ended, Buffered Voltage Output Configuration........ 16
Power and Grounding Considerations, Power Supply
Rejection...................................................................................... 17
Evaluation Board ............................................................................ 18
General Description................................................................... 18
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Changes to Functional Description, Reference Operation, and
Reference Control Amplifier Sections......................................... 11
Inserted Figure 16; Renumbered Sequentially ........................... 11
Changes to DAC Transfer Function Section............................... 12
Changes to Digital Inputs Section................................................ 13
Changes to Figure 22, Figure 23, and Figure 24 ......................... 14
Changes to Figure 25...................................................................... 15
Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 16
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
2/03—Revision 0: Initial Version
Rev. B | Page 2 of 24

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Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (External Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)4
Clock Supply Current (ICLKVDD)
Supply Current Sleep Mode (IAVDD)
Power Dissipation4
Power Dissipation5
Power Supply Rejection Ratio—AVDD6
Power Supply Rejection Ratio—DVDD6
OPERATING RANGE
Min
8
±0.25
±0.25
−0.02
−0.5
−0.5
2.0
−1.0
1.14
0.1
Typ
±0.1
±0.1
±0.1
±0.1
100
5
1.20
100
7
0.5
0
±50
±100
±50
Max
+0.25
+0.25
+0.02
+0.5
+0.5
20.0
+1.25
1.26
1.25
2.7
2.7
2.7
−1
−0.04
−40
3.3
3.3
3.3
33
8
5
5
135
145
3.6
3.6
3.6
36
9
7
6
145
+1
+0.04
+85
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4 Measured at fCLOCK = 100 MSPS and fOUT = 1 MHz.
5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz.
6 ±5% power supply variation.
AD9748
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
kΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
Rev. B | Page 3 of 24

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AD9748
Data Sheet
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly
terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)2
Output Noise (IOUTFS = 2 mA)2
AC LINEARITY
Signal-to-Noise and Distortion Ratio
fCLOCK = 50 MSPS; fOUT = 5 MHz
fCLOCK = 50 MSPS; fOUT = 19 MHz
fCLOCK = 100 MSPS; fOUT = 5 MHz
fCLOCK = 100 MSPS; fOUT = 39 MHz
fCLOCK = 165 MSPS; fOUT = 5 MHz
fCLOCK = 165 MSPS; fOUT = 49 MHz
fCLOCK = 210 MSPS; fOUT = 9 MHz
fCLOCK = 210 MSPS; fOUT = 68 MHz
Total Harmonic Distortion
fCLOCK = 25 MSPS; fOUT = 1 MHz
fCLOCK = 50 MSPS; fOUT = 12.5 MHz
fCLOCK = 100 MSPS; fOUT = 25 MHz
fCLOCK = 165 MSPS; fOUT = 41.3 MHz
fCLOCK = 210 MSPS; fOUT = 68 MHz
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 25 MSPS; fOUT = 1 MHz
0 dBFS Output
fCLOCK = 65 MSPS; fOUT = 5 MHz
fCLOCK = 65 MSPS; fOUT = 19 MHz
fCLOCK = 100 MSPS; fOUT = 5 MHz
fCLOCK = 100 MSPS; fOUT = 39 MHz
fCLOCK = 165 MSPS; fOUT = 5 MHz
fCLOCK = 165 MSPS; fOUT = 49 MHz
fCLOCK = 210 MSPS; fOUT = 5 MHz
fCLOCK = 210 MSPS; fOUT = 68 MHz
Min Typ Max
210
11
1
5
2.5
2.5
50
30
50
48
50
46
50
47
50
46
−72 −61
−65
−60
−58
−65
61 72
69
65
68
62
68
54
67
60
1 Measured single-ended into 50 Ω load.
2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
Unit
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
dB
dB
dB
dB
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. B | Page 4 of 24