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Data Sheet
4 CML Output, Low Jitter Clock Generator
with an Integrated 5.4 GHz VCO
AD9530
FEATURES
Fully integrated, ultralow noise phase-locked loop (PLL)
4 differential, 2.7 GHz common-mode logic (CML) outputs
2 differential reference inputs with programmable internal
termination options
<232 fs rms absolute jitter (12 kHz to 20 MHz) with a non-
ideal reference and 8 kHz loop bandwidth
<100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz
loop bandwidth and low jitter input reference clock
Supports low loop bandwidths for jitter attenuation
Manual switchover
Single 2.5 V typical supply voltage
48-lead, 7 mm × 7 mm LFCSP
APPLICATIONS
40 Gbps/100 Gbps optical transport network (OTN) line side
clocking
Clocking of high speed analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs)
Data communications
GENERAL DESCRIPTION
The AD9530 is a fully integrated PLL and distribution supporting,
clock cleanup, and frequency translation device for 40 Gbps/
100 Gbps OTN applications. The internal PLL can lock to one
of two reference frequencies to generate four discrete output
frequencies up to 2.7 GHz.
The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow
noise voltage controlled oscillator (VCO). All four outputs are
individually divided down from the internal VCO using two high
speed VCO dividers (the Mx dividers) and four individual 8-bit
channel dividers (the Dx dividers). The high speed VCO dividers
offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of
possible output frequencies. The AD9530 is configurable for
loop bandwidths <15 kHz to attenuate reference noise.
The AD9530 is available in a 48-lead LFCSP and operates from a
single 2.5 V typical supply voltage.
The AD9530 operates over the extended industrial temperature
range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
AD9530
REFA
REFA
REFB
REFB
800MHz MAX
R DIVIDER
(1 TO 255)
PLL
SERIAL PORT AND
CONTROL LOGIC
M1 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
M2 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
D1 DIVIDER
(1 TO 255)
D2 DIVIDER
(1 TO 255)
D3 DIVIDER
(1 TO 255)
D4 DIVIDER
(1 TO 255)
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
SDIO SDO SCLK CS
LD
Figure 1.
CML 50Ω SOURCE TERMINATED
2.7GHz MAX
Rev. 0
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AD9530 Evaluation Board
DOCUMENTATION
Data Sheet
AD9530: 4 CML Output, Low Jitter Clock Generator with
an Integrated 5.4 GHz VCO Data Sheet
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AD9530 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
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AD9530
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Supply Voltage and Temperature Range.................................... 4
Supply Current.............................................................................. 4
Power Dissipation......................................................................... 5
REFA and REFB Input Characteristics...................................... 6
PLL Characteristics ...................................................................... 7
PLL Digital Lock Detect .............................................................. 7
Clock Outputs (Internal Termination Disabled) ..................... 7
Clock Outputs (Internal Termination Enabled)....................... 8
Clock Output Absolute Time Jitter (Low Loop
Bandwidth).................................................................................... 9
Clock Output Absolute Time Jitter (High Loop
Bandwidth).................................................................................. 10
RESET and REF_SEL Pins ........................................................ 10
LD Pin .......................................................................................... 10
Serial Control Port ..................................................................... 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Detailed Functional Block Diagram ........................................ 18
Overview...................................................................................... 18
Configuration of the PLL .......................................................... 18
Reset Modes ................................................................................ 21
Power-Down Modes................................................................... 21
Input/Output Termination Recommendations .......................... 22
Serial Control Port.......................................................................... 23
SPI Serial Port Operation .......................................................... 23
Power Dissipation and Thermal Considerations ....................... 26
Clock Speed and Driver Mode ................................................. 26
Evaluation of Operating Conditions........................................ 26
Thermally Enhanced Package Mounting Guidelines ............ 26
Applications Information .............................................................. 27
Power Supply Recommendations............................................. 27
Using the AD9530 Outputs for ADC Clock Applications .... 27
Typical Application Block Diagram......................................... 28
Control Registers ............................................................................ 29
Control Register Map Overview .............................................. 29
Control Register Map Descriptions ............................................. 31
SPI Configuration (Register 0x000 to Register 0x001) ......... 31
Status (Register 0x002) .............................................................. 32
Chip Type (Register 0x003) ...................................................... 32
Product ID (Register 0x004 to Register 0x005)...................... 32
Part Version (Register 0x006)................................................... 33
User Scratchpad 1 (Register 0x00A) ........................................ 33
SPI Version (Register 0x00B).................................................... 33
Vendor ID (Register 0x00C to Register 0x00D)..................... 33
IO_UPDATE (Register 0x00F)................................................. 33
R Divider (Reference Input Divider) (Register 0x010) ......... 33
R Divider Control (Register 0x011)......................................... 34
Reference Input A (Register 0x012)......................................... 34
Reference Input B (Register 0x013) ......................................... 34
OUT1 Divider (Register 0x014) ............................................... 35
OUT1 Driver Control Register (Register 0x015)................... 35
OUT2 Divider (Register 0x016) ............................................... 35
OUT2 Driver Control (Register 0x017) .................................. 35
OUT3 Divider (Register 0x018) ............................................... 36
OUT3 Driver Control (Register 0x019) .................................. 36
OUT4 Divider (Register 0x01A) .............................................. 36
OUT4 Driver Control (Register 0x01B).................................. 36
VCO Power (Register 0x01C)................................................... 37
PLL Lock Detect Control (Register 0x01D) ........................... 37
PLL Lock Detect Readback (Registers 0x01E to 0x01F)....... 37
M1, M2, M3 Dividers (Register 0x020 to Register 0x022) ... 38
M3 Divider (Register 0x022) .................................................... 39
N Divider (Register 0x023) ....................................................... 39
N Divider Control (Register 0x024) ........................................ 39
Charge Pump (Register 0x025) ................................................ 39
Phase Frequency Dectector (Register 0x026)......................... 39
Loop Filter (Register 0x027) ..................................................... 40
VCO Frequency (Register 0x028) ............................................ 40
User Scratchpad2 (Register 0x0FE) ......................................... 40
Rev. 0 | Page 2 of 41

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Data Sheet
User Scratchpad3 (Register 0x0FF) ..........................................40
Outline Dimensions........................................................................41
REVISION HISTORY
4/16—Revision 0: Initial Version
AD9530
Ordering Guide ...........................................................................41
Rev. 0 | Page 3 of 41

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AD9530
Data Sheet
SPECIFICATIONS
Typical values are given for VDD = 2.5 V ± 5%, TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD
range and TA (−40°C to +85°C) variations listed in Table 1.
SUPPLY VOLTAGE AND TEMPERATURE RANGE SPECIFICATIONS
Table 1.
Parameter
SUPPLY VOLTAGE
TEMPERATURE
Ambient Temperature Range
Junction Temperature1
Symbol Min Typ Max Unit Test Conditions/Comments
VDD
2.375 2.5 2.625 V
2.5 V ± 5%
TA −40 +25 +85 °C
TJ 115 °C
1 The is the maximum junction temperature for which device performance is guaranteed. Note that the Absolute Maximum Ratings section may have a higher
maximum junction temperature, but device operation or performance is not guaranteed above the number that appears here. To calculate the junction temperature,
see the Power Dissipation and Thermal Considerations section.
SUPPLY CURRENT SPECIFICATIONS
Table 2.
Parameter
SUPPLY CURRENT OTHER THAN CLOCK THE
DISTRIBUTION CHANNEL
Typical Operation 1
Reference Input VDD (Pin 3 and Pin 7)
PLL VDD (Pin 12)
Rotary Travelling Wave Oscillator (RTWO) VDD
(Pin 20 to Pin 23)
SUPPLY CURRENT FOR AN INDIVIDUAL CLOCK
DISTRIBUTION CHANNEL
CML
Internal Termination Disabled
800 mV
900 mV
1000 mV
1100 mV
Internal Termination Enabled
800 mV
900 mV
1000 mV
1100 mV
Min Typ Max Unit Test Conditions/Comments
Current listed in the Typ column is at nominal VDD at
25°C; current listed in the Max column is at
maximum VDD and worst case temperature
fRTWO = 5300.16 MHz; VCO mode = low power;
REFA enabled at 110.42 MHz; REFB disabled;
R divider = 1; M1 and M3 divider = 3; M2 divider =
powered down; phase frequency detector (PFD) =
110.42 MHz; OUT1 CML output at 1766.72 MHz;
OUT2, OUT3, and OUT4 outputs and dividers
powered down; single-ended output swing level =
800 mV; outputs terminated externally with 50 Ω
to VDD
8.2 10.7 mA
Combined current of Pin 3 and Pin 7
18.2 24
mA
747 860 mA
Combined current of Pin 20 to Pin 23
Each output channel has a dedicated VDD pin; all
current values are listed for a single driver supply
pin operating at 1766.72 MHz; output terminated
externally, 50 Ω to VDD; these specifications include
the current required for the external load resistors
28.8 35.5 mA
30.7 37.6 mA
32.6 39.8 mA
34.5 41.8 mA
47.6 57.2 mA
51.5 61.5 mA
55.3 65.8 mA
59.0 70.1 mA
Rev. 0 | Page 4 of 41