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Data Sheet
Jitter Cleaner and Clock Generator with
14 Differential or 29 LVCMOS Outputs
AD9523
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <150 ps
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <50 ps
Duty cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <200 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Distribution phase noise floor: −160 dBc/Hz
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate up to 259 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
REFA,
REFA
REFB,
REFB
REF_TEST
OSC_IN, OSC_IN
PLL1
PLL2
AD9523
OUT0,
OUT0
OUT1,
OUT1
SCLK/SCL
SDIO/SDA
SDO
CONTROL
INTERFACE
(SPI AND I2C)
ZERO
DELAY
EEPROM
14-CLOCK
DISTRIBUTION
OUT12,
OUT12
OUT13,
OUT13
ZD_IN, ZD_IN
Figure 1.
GENERAL DESCRIPTION
The AD9523 provides a low power, multi-output, clock distribution
function with low jitter performance, along with an on-chip PLL
and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.
The AD9523 is designed to support the clock requirements for long
term evolution (LTE) and multicarrier GSM base station designs.
It relies on an external VCXO to provide the reference jitter cleanup
to achieve the restrictive low phase noise requirements necessary
for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free coarse timing adjustment in
increments that are equal to half the period of the signal coming
out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up and
chip reset.
Rev. D
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AD9523* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
AD9523/AD9523-1 Evaluation Board
DOCUMENTATION
Application Notes
AN-1066: Power Supply Considerations for AD9523,
AD9524, and AD9523-1 Low Noise Clocks
Data Sheet
AD9523: Jitter Cleaner and Clock Generator with 14
Differential or 29 LVCMOS Outputs Data Sheet
User Guides
UG-169: Evaluating the AD9523/AD9524 Clock Generator
SOFTWARE AND SYSTEMS REQUIREMENTS
AD9523 Low Jitter Clock Generator Linux Driver
TOOLS AND SIMULATIONS
ADIsimCLK Design and Evaluation Software
AD9523/AD9523-1 IBIS Model
REFERENCE MATERIALS
Customer Case Studies
Datang Mobile Case Study
Product Selection Guide
RF Source Booklet
Technical Articles
Dual-Loop Clock Generator Cleans Jitter, Provides
Multiple High-Frequency Outputs
DESIGN RESOURCES
AD9523 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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AD9523
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Conditions ..................................................................................... 4
Supply Current.............................................................................. 4
Power Dissipation......................................................................... 5
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, and ZD_IN,
ZD_IN Input Characteristics ...................................................... 5
OSC_CTRL Output Characteristics .......................................... 6
REF_TEST Input Characteristics ............................................... 6
PLL1 Characteristics .................................................................... 6
PLL1 Output Characteristics ...................................................... 6
Distribution Output Characteristics (OUT0, OUT0 to
OUT13, OUT13) .......................................................................... 7
Timing Alignment Characteristics ............................................ 8
Jitter and Noise Characteristics .................................................. 8
PLL2 Characteristics .................................................................... 8
Logic Input Pins—PD, EEPROM_SEL, REF_SEL, RESET,
SYNC.............................................................................................. 9
Status Output Pins—STATUS1, STATUS0 ............................... 9
Serial Control Port—SPI Mode .................................................. 9
Serial Control Port—I²C Mode ................................................ 10
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
Input/Output Termination Recommendations .......................... 17
Terminology .................................................................................... 18
Data Sheet
Theory of Operation ...................................................................... 19
Detailed Block Diagram ............................................................ 19
Overview ..................................................................................... 19
Component Blocks—Input PLL (PLL1).................................. 20
Component Blocks—Output PLL (PLL2) .............................. 22
Clock Distribution ..................................................................... 24
Zero Delay Operation................................................................ 26
Lock Detect ................................................................................. 26
Reset Modes ................................................................................ 26
Power-Down Mode .................................................................... 27
Power Supply Sequencing ......................................................... 27
Serial Control Port ......................................................................... 28
SPI/I²C Port Selection................................................................ 28
I²C Serial Port Operation .......................................................... 28
SPI Serial Port Operation .......................................................... 31
SPI Instruction Word (16 Bits)................................................. 32
SPI MSB/LSB First Transfers .................................................... 32
EEPROM Operations..................................................................... 35
Writing to the EEPROM ........................................................... 35
Reading from the EEPROM ..................................................... 35
Programming the EEPROM Buffer Segment......................... 36
Device Initialization Flow Charts................................................. 38
Power Dissipation and Thermal Considerations ....................... 41
Clock Speed and Driver Mode ................................................. 41
Evaluation of Operating Conditions........................................ 41
Thermally Enhanced Package Mounting Guidelines............ 42
Control Registers ............................................................................ 43
Control Register Map ................................................................ 43
Control Register Map Bit Descriptions ................................... 48
Outline Dimensions ....................................................................... 60
Ordering Guide .......................................................................... 60
Rev. D | Page 2 of 60

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Data Sheet
REVISION HISTORY
9/15—Rev. C to Rev. D
Changes to Features Section ............................................................1
Changes to Table 7 ............................................................................6
Changes to Table 12 ..........................................................................8
Added Operating Temperature Range Parameter and Junction
Temperature Parameter, Table 17..................................................11
Changes to Figure 21 ......................................................................17
Changes to Figure 22 and Overview Section...............................19
Changes to PLL1 Reference Clock Inputs Section and PLL1
Loop Filter Section ..........................................................................20
Added OSC_IN Input Section.......................................................20
Changes to PLL2 General Description Section...........................22
Changes to VCO and VCO Calibration Section .........................23
Changes to Zero Delay Operation Section ..................................26
Added Power Supply Sequencing Section ...................................27
Deleted Figure 32; Renumbered Sequentially .............................29
Changes to SPI Instruction Word (16 Bits) Section ...................32
Changes to Writing to the EEPROM Section and Reading from
the EEPROM Section......................................................................35
Changes to Programming the EEPROM Buffer Segment
Section ..............................................................................................36
Added Device Initialization Flow Charts Section, Figure 44, and
Figure 45; Renumbered Sequentially............................................38
Changes to Table 31 ........................................................................44
Changes to Table 40 ........................................................................49
Changes to Table 47 ........................................................................52
2/13—Rev. B to Rev. C
Deleted VDD1.8_PLL2................................................. Throughout
Changes to Data Sheet Title .............................................................1
Added TJ of 115°C, Table 1 ..............................................................4
Changed VDD3_PLL1, Supply Voltage for PLL1 Typical
Parameter from 22 mA to 37 mA and Changed VDD3_PLL1,
Supply Voltage for PLL1 Maximum Parameter from 25.2 mA to
43 mA, Table 2 ...................................................................................4
Changes to Table 3 ............................................................................5
Added PLL1 Characteristics Section and Table 7; Renumbered
Sequentially ........................................................................................6
Changes to Table 9 Summary Statement........................................7
Changes to Pin 7 Description, Table 19 .......................................13
Changed Pin 69 from VDD1.8_PLL2 to NC, Table 19 ..............15
Changes to Figure 23 ......................................................................21
Changes to Clock Distribution Synchronization Section ..........25
Changes to Figure 29 ......................................................................26
Added Reset Modes Section and Lock Detect Section ..............26
Added Power-Down Mode Section ..............................................27
AD9523
Changes to Pin Descriptions Section and Read Section............31
Added Figure 38; Renumbered Sequentially...............................33
Changes to Register Section Definition Group Section ............36
Changes to Power Dissipation and Thermal Considerations
Section ..............................................................................................38
Changes to Table 31 ........................................................................40
Changes to Bits[1:0] Description, Table 40 and Bit 2
Description, Table 41 ......................................................................46
Changes to Bits[7:6] Description, Table 42 .................................47
Changes to Bits[1:0] Description, Table 43 .................................48
Changes to Bit 4, Bits [3:2] Descriptions, Table 47.....................49
Changed Bit 6 Name from Status PLL2 Feedback Clock to Status
PLL1 Feedback Clock, Table 54 ......................................................52
3/11—Rev. A to Rev. B
Added Table Summary, Table 8.......................................................7
Changes to EEPROM Operations Section and Writing to the
EEPROM Section ............................................................................34
Changes to 0x01A, Bits[4:3], Table 30..........................................39
Changes to Bits[4:3], Table 40 .......................................................46
Changes to Table 47, Bit 1 ..............................................................48
11/10—Rev. 0 to Rev. A
Change to General Description.......................................................1
Changes to Table Summary, Table 1 ...............................................3
Change to Input High Voltage and Input Low Voltage
Parameters and Added Input Threshold Voltage Parameter,
Table 4.................................................................................................4
Change to Junction Temperature Rating, Table 16; Changes
to Thermal Resistance Section ......................................................11
Changes to Table 18 ........................................................................12
Added Figure 14, Renumbered Sequentially...............................16
Edits to Figure 15, Figure 17, and Figure 19................................17
Changes to VCO Calibration Section...........................................22
Changed Output Mode Heading to Multimode Output
Drivers; Changes to Multimode Output Drivers Section;
Added Figure 26 ..............................................................................23
Added Power Dissipation and Thermal Considerations
Section; Added Table 29, Renumbered Sequentially..................35
Changes to Table 34, Table 35, Table 36, and Table 38...............43
Changes to Address 0x192, Table 50 ............................................48
Changes to Table 52 ........................................................................49
Changes to Table 54 ........................................................................50
7/10—Revision 0: Initial Version
Rev. D | Page 3 of 60

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AD9523
Data Sheet
SPECIFICATIONS
fVCXO = 122.88 MHz single ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control low
power mode off, divider phase = 1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5% and TA = 25°C, unless otherwise noted.
Minimum and maximum values are given over the full VDD and TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1
3.3 V 3.3 V ± 5%
VDD3_PLL2, Supply Voltage for PLL2
3.3 V 3.3 V ± 5%
VDD3_REF, Supply Voltage Clock Output Drivers Reference
3.3
V 3.3 V ± 5%
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
3.3 V 3.3 V ± 5%
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
1.8 V 1.8 V ± 5%
TEMPERATURE
Ambient Temperature Range, TA
−40 +25 +85 °C
Junction Temperature, TJ
115 °C
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
SUPPLY CURRENT
Table 2.
Parameter
Min Typ Max Unit Test Conditions/Comments
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1
37 43
mA Decreases by 9 mA typical if REFB is turned off
VDD3_PLL2, Supply Voltage for PLL2
67 77.7 mA
VDD3_REF, Supply Voltage Clock Output Drivers Reference
LVPECL Mode
56
mA Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
LVDS Mode
4 4.8 mA Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
HSTL Mode
3 3.6 mA Values are independent of the number of
outputs turned on
CMOS Mode
3 3.6 mA Values are independent of the number of
outputs turned on
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2
3.5 4.2 mA Current for each divider: f = 245.76 MHz
CLOCK OUTPUT DRIVERS
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
16 17.4 mA f = 61.44 MHz
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
5 6.2 mA f = 245.76 MHz
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
17 18.9 mA f = 122.88 MHz
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
21 24.0 mA f = 122.88 MHz
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
14 16.3 mA f = 122.88 MHz
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
2 2.4 mA f = 15.36 MHz, 10 pF load
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
2 The current for Pin 63 (VDD1_OUT[0:3]) is 2× that of the other VDD11.8_OUT[x:y] pairs.
Rev. D | Page 4 of 60