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Data Sheet
Low Jitter Clock Generator with
14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9523-1
FEATURES
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <150 ps
Dual VCO dividers
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <50 ps
Duty cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <150 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Broadband timing jitter: 124 fs
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to 130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate up to 259 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
FUNCTIONAL BLOCK DIAGRAM
REFA,
REFA
REFB,
REFB
REF_TEST
OSC_IN, OSC_IN
AD9523-1
PLL1
PLL2
DIVIDE-BY-
3, 4, 5
8 OUTPUTS
OUT0,
OUT0
OUT3,
OUT3
OUT10,
OUT10
OUT13,
OUT13
SCLK/SCL
SDIO/SDA
SDO
CONTROL
INTERFACE
(SPI AND I2C)
DIVIDE-BY-
3, 4, 5
ZERO
DELAY
EEPROM
6 OUTPUTS
14-CLOCK
DISTRIBUTION
ZD_IN, ZD_IN
Figure 1.
OUT4,
OUT4
OUT9,
OUT9
GENERAL DESCRIPTION
The AD9523-1 provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO with two VCO dividers. The on-chip VCO
tunes from 2.94 GHz to 3.1 GHz.
The AD9523-1 is designed to support the clock requirements
for long term evolution (LTE) and multicarrier GSM base
station designs. It relies on an external VCXO to provide the
reference jitter cleanup to achieve the restrictive low phase noise
requirements necessary for acceptable data converter SNR
performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free, coarse timing adjustment
in increments that are equal to half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up
and chip reset.
Rev. C
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AD9523-1* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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EVALUATION KITS
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DOCUMENTATION
Application Notes
AN-1066: Power Supply Considerations for AD9523,
AD9524, and AD9523-1 Low Noise Clocks
Data Sheet
AD9523-1: Low Jitter Clock Generator with14 LVPECL/
LVDS/HSTL/29 LVCMOS Outputs
User Guides
UG-182: Evaluation Board User Guide for AD9523-1 Clock
Generator
SOFTWARE AND SYSTEMS REQUIREMENTS
AD9523 Low Jitter Clock Generator Linux Driver
TOOLS AND SIMULATIONS
ADIsimCLK Design and Evaluation Software
AD9523/AD9523-1 IBIS Model
REFERENCE MATERIALS
Product Selection Guide
RF Source Booklet
Technical Articles
Dual-Loop Clock Generator Cleans Jitter, Provides
Multiple High-Frequency Outputs
DESIGN RESOURCES
AD9523-1 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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AD9523-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Conditions ..................................................................................... 4
Supply Current.............................................................................. 4
Power Dissipation......................................................................... 6
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, and ZD_IN,
ZD_IN Input Characteristics ...................................................... 7
OSC_CTRL Output Characteristics .......................................... 7
REF_TEST Input Characteristics ............................................... 7
PLL1 Output Characteristics ...................................................... 8
OUT0, OUT0 to OUT13, OUT13 Distribution Output
Characteristics .............................................................................. 8
Timing Alignment Characteristics ............................................ 9
Jitter and Noise Characteristics ................................................ 10
PLL2 Characteristics .................................................................. 10
Logic Input Pins—PD, SYNC, RESET, EEPROM_SEL,
REF_SEL ...................................................................................... 10
Status Output Pins—STATUS1, STATUS0 ............................. 11
Serial Control Port—SPI Mode ................................................ 11
Serial Control Port—I²C Mode ................................................ 12
Absolute Maximum Ratings.......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 17
Input/Output Termination Recommendations .......................... 20
Terminology .................................................................................... 21
Data Sheet
Theory of Operation ...................................................................... 22
Detailed Block Diagram ............................................................ 22
Overview ..................................................................................... 22
Component Blocks—Input PLL (PLL1).................................. 23
Component Blocks—Output PLL (PLL2) .............................. 24
Clock Distribution ..................................................................... 26
Zero Delay Operation................................................................ 28
Lock Detect ................................................................................. 28
Reset Modes ................................................................................ 28
Power-Down Mode .................................................................... 29
Power Supply Sequencing ......................................................... 29
Serial Control Port ......................................................................... 30
SPI/I²C Port Selection................................................................ 30
I²C Serial Port Operation .......................................................... 30
SPI Serial Port Operation .......................................................... 33
SPI Instruction Word (16 Bits)................................................. 34
SPI MSB/LSB First Transfers .................................................... 34
EEPROM Operations..................................................................... 37
Writing to the EEPROM ........................................................... 37
Reading from the EEPROM ..................................................... 37
Programming the EEPROM Buffer Segment......................... 38
Device Initialization Flowcharts................................................... 40
Power Dissipation and Thermal Considerations ....................... 43
Clock Speed and Driver Mode ................................................. 43
Evaluation of Operating Conditions........................................ 43
Thermally Enhanced Package Mounting Guidelines............ 44
Control Registers ............................................................................ 45
Control Register Map ................................................................ 45
Control Register Map Bit Descriptions ................................... 50
Outline Dimensions ....................................................................... 63
Ordering Guide .......................................................................... 63
Rev. C | Page 2 of 63

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Data Sheet
REVISION HISTORY
9/15—Rev. B to Rev. C
Changes to Features Section ............................................................1
Added Junction Temperature, TJ Parameter, Table 1 ...................4
Changes to Table 7 ............................................................................8
Changes to Table 11 ........................................................................10
Changes to Figure 23 ......................................................................20
Changes to Overview Section........................................................22
Added OSC_IN Input Section.......................................................23
Changes to PLL1 Loop Filter Section ...........................................23
Changed VCXO to OSC_IN, VCO Calibration Section............25
Changes to Clock Distribution Synchronization Section ..........27
Changes to Zero Delay Operation Section ..................................28
Added Lock Detect Section and Reset Modes Section ..............28
Added Power-Down Mode Section and Power Supply
Sequencing Section .........................................................................29
Changes to Read Section ................................................................33
Changes to Writing to the EEPROM Section..............................37
Changes to Reading from the EEPROM Section and
Programming the EEPROM Buffer Segment Section................38
Added Device Initialization Flowcharts Section, Figure 46, and
Figure 47; Renumbered Sequentially............................................40
Changes to Power Dissipation and Thermal Considerations
Section and Evaluation of Operating Conditions Section.........43
Changes to Example 2 Section.......................................................44
Changes to Table 39 ........................................................................51
Changes to Table 46 ........................................................................54
Updated Outline Dimensions........................................................63
AD9523-1
3/11—Rev. A to Rev. B
Added Table Summary, Table 8.......................................................7
Changes to Figure 24 ......................................................................21
Changes to EEPROM Operations Section and Writing to the
EEPROM Section ............................................................................35
Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30 ....................40
Changes to Bits[4:3], Table 40 .......................................................47
12/10—Rev. 0 to Rev. A
Changes to General Description Section .......................................1
Changes to Frequency Range, Table 11..........................................9
Changes to PLL2 General Description Section...........................23
Changes to Table 47, Address 0x0F3, Bit 1 ..................................48
10/10—Revision 0: Initial Version
Rev. C | Page 3 of 63

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AD9523-1
Data Sheet
SPECIFICATIONS
fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 2949.12 MHz, doubler is on, unless otherwise noted.
Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD and
TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
VDD3_PLL, Supply Voltage for PLL1 and PLL2
VDD3_VCO, Supply Voltage for VCO
VDD3_REF, Supply Voltage Clock Output Drivers Reference
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
AMBIENT TEMPERATURE RANGE, TA
JUNCTION TEMPERATURE, TJ
Min Typ
3.135
3.135
3.135
3.135
1.768
−40
3.3
3.3
3.3
3.3
1.8
+25
Max Unit Test Conditions/Comments
3.465
3.465
3.465
3.465
1.832
+85
+115
V
V
V
V
V
°C
°C
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
1.8 V ± 5%
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
SUPPLY CURRENT
Table 2.
Parameter
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL, Supply Voltage for PLL1 and PLL2
VDD3_VCO, Supply Voltage for VCO and VCO Divider M1
VDD3_REF, Supply Voltage Clock Output Drivers Reference
VCO Divider M1 Enabled
LVPECL Mode, LVDS Mode
Min
HSTL Mode, CMOS Mode
VCO Divider M2 Enabled
LVPECL Mode, LVDS Mode
HSTL Mode, CMOS Mode
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
Typ Max
37 41.9
70 75.8
4 5.1
3 3.6
26 30.1
24.5 28.6
3.2 5.8
6.4 12
11.5 13.2
40 45
6.5 7.5
23 26.3
13 14.4
41 46.5
Unit Test Conditions/Comments
mA Decreases by 9 mA typical if REFB is turned off
mA All outputs use VCO Divider M1
mA Use VCO Divider M1; only one output driver
is turned on; for each additional output that
is turned on, the current increments by 1.2 mA
maximum
mA Use VCO Divider M1; values are independent
of the number of outputs turned on
mA Use VCO Divider M2; only one output driver
is turned on; for each additional output that
is turned on, the current increments by 1.2 mA
maximum
mA Use VCO Divider M2; values are independent
of the number of outputs turned on
mA Current for each divider: f = 122.88 MHz
mA Current for each divider: f = 983.04 MHz
Channel x control register, Bit 4 = 0
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
mA f = 122.88 MHz
mA f = 983.04 MHz
Rev. C | Page 4 of 63