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Data Sheet
Octal LNA/VGA/AAF/ADC
and CW I/Q Demodulator
AD9278
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low power: 88 mW per channel, TGC mode, 40 MSPS;
32 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP-BGA
TGC channel input-referred noise: 1.3 nV/Hz, max gain
Flexible power-down modes
Fast recovery from low power standby mode: <2 μs
Overload recovery: <10 ns
Low noise preamplifier (LNA)
Input-referred noise: 1.25 nV/√Hz, gain = 21.3 dB
Programmable gain: 15.6 dB/17.9 dB/21.3 dB
0.1 dB compression: 1000 mV p-p/
750 mV p-p/450 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW): >50 MHz
Variable gain amplifier (VGA)
Attenuator range: −45 dB to 0 dB
Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
SNR: 70 dB, 12 bits up to 65 MSPS
Serial LVDS (ANSI-644, low power/reduced signal)
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel: >158 dBc/√Hz
Output-referred SNR: 153 dBc/√Hz, 1 kHz offset, −3 dBFS
GENERAL DESCRIPTION
The AD9278 is designed for low cost, low power, small size,
and ease of use for medical ultrasound and automotive radar. It
contains eight channels of a variable gain amplifier (VGA) with
a low noise preamplifier (LNA), an antialiasing filter (AAF), an
analog-to-digital converter (ADC), and an I/Q demodulator
with programmable phase rotation.
Each channel features a variable gain range of 45 dB, a fully
differential signal path, an active input preamplifier termination,
and a maximum gain of up to 51 dB. The channel is optimized
for high dynamic performance and low power in applications
where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. Assuming a 15 MHz noise bandwidth (NBW)
and a 21.3 dB LNA gain, the LNA input SNR is roughly 88 dB.
In CW Doppler mode, each LNA output drives an I/Q demod-
ulator that has independently programmable phase rotation
with 16 phase settings.
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
several features designed to maximize flexibility and minimize
system cost, such as a programmable clock, data alignment, and
programmable digital test pattern generation. The digital test
patterns include built-in fixed patterns, built-in pseudo random
patterns, and custom user-defined test patterns entered via the
serial port interface.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
I/Q
DEMODULATOR
VGA
AAF
8 CHANNELS
12-BIT
ADC
SERIAL
LVDS
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
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Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.

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AD9278* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
AD9278 Evaluation Board
DOCUMENTATION
Data Sheet
AD9278: Octal LNA/VGA/AAF/ADC and CW I/Q
Demodulator
TOOLS AND SIMULATIONS
Visual Analog
REFERENCE MATERIALS
Press
• Industry’s First Octal Ultrasound Receiver with Digital I/Q
Demodulator and Decimation Filter Reduces Processor
Overhead in Ultrasound Systems
Low Cost, Octal Ultrasound Receiver with On-Chip RF
Decimator and JESD204B Serial Interface
Technical Articles
MS-2210: Designing Power Supplies for High Speed ADC
DESIGN RESOURCES
AD9278 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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AD9278
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 3
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
ADC Timing Diagrams ............................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Impedance ..................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 13
TGC Mode................................................................................... 13
CW Doppler Mode..................................................................... 16
REVISION HISTORY
/12—Rev. 0 to Rev. A
Changes to SNR in Features Section.............................................. 1
Added Mode IV to Table 1 and Table 1 Conditions .................... 3
Added Mode IV Clock Rate Parameters and Changed tEH and tEL
from 6.25 ns to 4.8 ns; Table 3 ................................................................... 7
Changes to Active Impedance Matching Section....................... 23
Added Table 9.................................................................................. 24
Changes to Figure 56 and Figure 57............................................. 28
Changes to Digital Outputs and Timing Section ....................... 30
Changes to 0x01 Bits[7:0] Description, Changes to 0x02 Bits[5:4]
Description and Default Value; Table 19..................................... 40
Updated Outline Dimensions ....................................................... 43
10/10—Revision 0: Initial Version
Data Sheet
Equivalent Circuits......................................................................... 17
Ultrasound Theory of Operation ................................................. 19
Channel Overview.......................................................................... 20
TGC Operation........................................................................... 20
CW Doppler Operation............................................................. 33
Serial Port Interface (SPI).............................................................. 37
Hardware Interface..................................................................... 37
Memory Map .................................................................................. 39
Reading the Memory Map Table.............................................. 39
Reserved Locations .................................................................... 39
Default Values ............................................................................. 39
Logic Levels................................................................................. 39
Outline Dimensions ....................................................................... 43
Ordering Guide .......................................................................... 43
Rev. A | Page 2 of 44

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Data Sheet
AD9278
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (−40°C to +85°C), fIN = 5 MHz,
RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.3 dB, LNA bias = default, PGA gain = 24 dB, GAIN− = 0.8 V, GAIN+ = 0 V, AAF LPF
cutoff = fSAMPLE/3 (MODE I/II/III), AAF LPF cutoff = fSAMPLE/4.5 (MODE IV), HPF cutoff = LPF cutoff/12, MODE I = fSAMPLE = 40 MSPS,
MODE II = fSAMPLE = 25 MSPS, MODE III = fSAMPLE = 50 MSPS, MODE IV = fSAMPLE = 65 MSPS, low power LVDS mode, unless otherwise
noted.
Table 1.
Parameter1
LNA CHARACTERISTICS
Gain
0.1 dB Input Compression Point
1 dB Input Compression Point
Input Common Mode (LI-x, LG-x)
Output Common Mode (LO-x)
Test Conditions/Comments
Single-ended input to differential
output
Single-ended input to single-ended
output
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
Min
Typ Max
15.6/17.9/21.3
9.6/11.9/15.3
1.00
0.75
0.45
1.20
0.90
0.60
2.2
Unit
dB
dB
V p-p
V p-p
V p-p
V p-p
V p-p
V p-p
V
V
Output Common Mode (LOSW-x)
Input Resistance (LI-x)
Input Capacitance (LI-x)
−3 dB Bandwidth
Input Noise Voltage
Input Noise Current
Noise Figure
Active Termination Matched
Unterminated
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF Low-Pass Cutoff
In Range AAF Bandwidth
Tolerance
Group Delay Variation
Switch off
Switch on
RFB = 350 Ω, LNA gain = 21.3 dB
RFB = 1400 Ω, LNA gain = 21.3 dB
RFB = ∞, LNA gain = 21.3 dB
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RFB = ∞
RS = 50 Ω
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
−3 dB, programmable
f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V
8
High-Z
1.5
50
200
15
22
100
80
50
1.60
1.42
1.27
1.5
7.8
6.7
5.6
6.1
5.3
4.7
±10
±0.3
18
Ω
V
kΩ
pF
MHz
MHz
MHz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
dB
dB
dB
dB
dB
dB
MHz
%
ns
Rev. A | Page 3 of 44

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AD9278
Parameter1
Input-Referred Noise Voltage
Noise Figure
Active Termination Matched
Unterminated
Correlated Noise Ratio
Output Offset
Signal-to-Noise Ratio (SNR)
Harmonic Distortion
Second Harmonic
Third Harmonic
Two-Tone Intermodulation (IMD3)
Channel-to-Channel Crosstalk
Channel-to-Channel Delay
Variation
PGA Gain
GAIN ACCURACY
Gain Law Conformance Error
Linear Gain Error
Channel-to-Channel Matching
GAIN CONTROL INTERFACE
Control Range
Gain Range
Scale Factor
Response Time
Gain+ Impedance
Gain− Impedance
CW DOPPLER MODE
LO Frequency
Phase Resolution
Output DC Bias (Single-Ended)
Output AC Current Range
Transconductance (Differential)
Test Conditions/Comments
GAIN+ = 1.6 V, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
GAIN+ = 1.6 V, RS = 50 Ω
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
No signal, correlated/uncorrelated
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V,
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,
ARF1 = 0 dB, ARF2 = −20 dB, GAIN+ =
1.6 VIMD3 relative to ARF2
fIN1 = 5.0 MHz at −1 dBFS
Overrange condition2
Full TGC path, fIN = 5 MHz, GAIN+ = 0 V to
1.6 V
Differential input to differential output
25°C
0 < GAIN+ < 0.16 V
0.16 V < GAIN+ < 1.44 V
1.44 V < GAIN+ < 1.6 V
GAIN+ = 0.8 V, normalized for ideal AAF
loss
0.16 V < GAIN+ < 1.44 V
Differential
Single-ended
GAIN+ = 0 V to 1.6 V
45 dB change
Single-ended
Single-ended
fLO = f4LO/4
Per channel
CWI+, CWI−, CWQ+, CWQ−
Per CWI+, CWI−, CWQ+, CWQ−, each
channel enabled
Demodulated IOUT/VIN, per CWI+, CWI−,
CWQ+, CWQ−
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
Rev. A | Page 4 of 44
Min
−35
−1.6
−1.6
−0.8
0
1
Data Sheet
Typ Max Unit
1.7 nV/√Hz
1.5 nV/√Hz
1.3 nV/√Hz
9.2 dB
7.7 dB
6.3 dB
6.7 dB
5.7 dB
4.9 dB
−30 dB
+35 LSB
65 dBFS
57 dBFS
−70 dBc
−70 dBc
−70 dBc
−70 dBc
−70 dBc
−60
−55
0.3
21/24/27/30
0.5
+1.6
0.5
+1.6
0.1
+0.8
1.6
45
28
750
10
70
10
22.5
1.5
±1.25
dB
dB
Degrees
dB
dB
dB
dB
dB
dB
V
V
dB
dB/V
ns
MHz
Degrees
V
mA
1.8 mA/V
2.4 mA/V
3.5 mA/V