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Multiple Linear Power Controller with
ACPI Control Interface
The ISL6506BIBZ complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates the control of the 5VDUAL and 3.3VDUAL rails into
an 8 Ld EPAD SOIC package. The ISL6506BIBZ operating
mode (active outputs or sleep outputs) is selectable through
two digital control pins; S3 and S5.
A completely integrated linear regulator generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output
during sleep states (S3, S4/S5). In active states (during S0
and S1/S2), the ISL6506BIBZ uses an external N-Channel
pass MOSFET to connect the outputs directly to the 3.3V
input supplied by an ATX power supply, for minimal losses.
The ISL6506BIBZ powers up the 5VDUAL plane by switching
in the ATX 5V output through an NMOS transistor in active
states, or by switching in the ATX 5VSB through a PMOS (or
PNP) transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6506BIBZ 5VDUAL output is shut down.
The ISL6506BIBZ features a 2A current limit on the internal
3.3V LDO.
September 12, 2013
ISL6506BI
FN7814.2
Features
• Provides 2 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
• Excellent 3.3VDUAL Regulation in S3/S4/S5
- ±2.0% Over-Temperature
- 2A Capability
• Small Size; Very Low External Component Count
• Over-Temperature Shutdown
• Pb-Free Available (RoHS Compliant)
Applications
ACPI-Compliant Power Regulation for Motherboards
- 5VDUAL is shut down in S4/S5 sleep states
Pinout
ISL6506BIBZ
(8 LD EPSOIC)
TOP VIEW
VCC 1
3V3AUX 2
S3 3
S5 4
GND
8 N/C
7 5VDLSB
6 DLA
5 GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6506BIBZ
6506B IBZ
-40 to +85
8 Ld EPSOIC
M8.15C
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6506BI. For more information on MSL please see techbrief TB363.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
DLA
ISL6506BI
VCC
S3 S5
5VDLSB
GND
3.5Ω
12V POR
SENSE
SOFT-START
7.5µA
MONITOR
AND
CONTROL
UV DETECTOR
10µA
10µA
TEMPERATURE
MONITOR
DIGITAL
( SOFT-START)
+
-
EA1
VCC
3V3AUX
Typical Application
5VSBY
12VATX 3V3ATX
5VSBY
5VATX
SLP_S3
SLP_S5
1kΩ
ISL6506BIBZ
1 VCC
2 3V3AUX
3 S3
4 S5
NC
5VDLSB
DLA
GND
8
7
6
5
9
Q1
Cg
(OPTIONAL)
Q2
Q3
5VDUAL
3V3DUAL
2 FN7814.2
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ISL6506BI
Absolute Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4000V
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +5.5V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
EPSOIC Package (Notes 4, 5) . . . . . .
40
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Recommended Operating Conditions. Boldface limits apply over the operating temperature range, -40°C
to +85°C.
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNITS
Nominal Supply Current
POWER-ON RESET
Rising 5VSB POR Threshold
I5VSB
VS3 = 5V, VS5 = 5V (S0 State)
VS3 = 0V, VS5 = 5V (S3 State)
VS5 = 0V (S5 State)
- 3.60 -
- 4.60 -
- 4.60 -
mA
mA
mA
-
- 4.5
V
Falling 5VSB POR Threshold
Rising 12V POR Threshold
3.3VAUX LINEAR REGULATOR
Regulation
3V3SB Nominal Voltage Level
3V3SB Undervoltage Threshold
3V3SB Overcurrent Trip
5VDUAL SWITCH CONTROLLER
5VDLSB Output Drive Current
TIMING INTERVAL
S0 to S3 Transition Delay
SOFT-START
Soft-start Interval
5VDLSB Soft-start Current Source
1.00kΩ resistor between DLA and 12V Rail
V5VSBY = 5.0V, I3V3SB = 0A
V3V3SB
V3V3SB_UV
I3V3SB_TRIP
I5VDLSB V5VDLSB = 4V, V5VSB = 5V
tSS
3.60 - 3.95
8.9 9.8 11
V
V
- - 2.0
- 3.3 -
- 2.5 -
- -2
%
V
V
A
20 - 35 mA
- 58 -
µs
6.55 8.2 9.85
- -7.5 -
ms
µA
CONTROL I/O (S3, S5)
High Level Input Threshold
Low Level Input Threshold
- - 2.2
0.8 -
-
V
V
S3, S5 Internal Pull-down Current to GND
- 10 -
µA
TEMPERATURE MONITOR
Shutdown-Level Threshold
- 140 -
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
°C
3 FN7814.2
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ISL6506BI
Functional Pin Description
VCC (Pin 1)
Provide a very well decoupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides all the bias for the IC as well as the input voltage for
the internal standby 3V3AUX LDO. The voltage at this pin is
monitored for power-on reset (POR) purposes.
GND (Pin 5, Pad)
Signal ground for the IC. These pins are also the ground
return for the internal 3V3AUX LDO that is active in
S3/S4/S5 sleep states. All voltage levels are measured with
respect to these pins.
S3 and S5 (Pins 3 and 4)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 10µA pull-down current sources on
each pin. Additional circuitry blocks illegal state transitions,
such as S4/S5 to S3. Connect S3 and S5 to the computer
system’s SLP_S3 and SLP_S5 signals, respectively.
3V3AUX (Pin 2)
Connect this pin to the 3V3DUAL output. In sleep states, the
voltage at this pin is regulated to 3.3V through an internal
pass device powered from 5VSBY through the VCC pin. In
active states, ATX 3.3V output is delivered to this node
through a fully-on NMOS transistor. During S3 and S4/S5
states, this pin is monitored for undervoltage events.
DLA (Pin 6)
This pin is an open-drain output. A 1kΩ resistor must be
connected from this pin to the ATX 12V output. This resistor
is used to pull the gates of suitable N-MOSFETs to 12V,
which in active state, switch in the ATX 3.3V and 5V outputs
into the 3.3VAUX and 5VDUAL outputs, respectively. This pin
is also used to monitor the 12V rail during POR. If a resistor
other than 1kΩ is used, the POR level will be affected.
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
In S3 sleep state, this transistor is switched on, connecting
the ATX 5VSB output to the 5VDUAL regulator output.
Description
Operation
The ISL6506BIBZ controls 2 output voltages, 3.3VDUAL and
5VDUAL. It is designed for microprocessor computer
applications requiring 3.3V, 5V, 5VSB, and 12V bias input
from an ATX power supply. The IC is composed of one linear
controller/regulator supplying the computer system’s
3.3VDUAL power, a dual switch controller supplying the
5VDUAL voltage, as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The ISL6506BIBZ automatically initializes upon receipt of
input power. The Power-On Reset (POR) function
continually monitors the 5VSB input supply voltage. The
ISL6506BIBZ also monitors the 12V rail to insure that the
ATX rails are up before entering into the S0 state even if
both SLP_S3 and SLP_S5 are both high.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
3.3VDUAL and 5VDUAL outputs. The internal circuitry does
not allow the transition from an S4/S5 state to an S3 state.
TABLE 1. 5VDUAL OUTPUT TRUTH TABLE
S5 S3 3.3AUX
5VDL
COMMENTS
11
3.3V
5V S0/S1/S2 States (Active)
10
3.3V
5V S3
01
Note
Maintains Previous State
00
3.3V
0V S4/S5
NOTE: Combination Not Allowed.
Functional Timing Diagram
Figure 1 is a simplified timing diagram, detailing the power-
up/down sequences of all the outputs in response to the status
of the sleep-state pins (S3, S5), as well as the status of the
input ATX supply. Not shown in this diagram is the deglitching
feature used to protect against false sleep state tripping.
Additionally, the ISL6506BIBZ features a 60µs delay in
transitioning from S0 to S3 states. The transition from the S0
state to S4/S5 state is immediate.
5VSB
S3
S5
3.3V, 5V, 12V
DLA
3V3AUX
5VDLSB
5VDL
FIGURE 1. 5VDUAL AND 3.3VAUX TIMING DIAGRAM;
ISL6506BIBZ
Soft-Start
Figures 2 and 3 show the soft-start sequence for the typical
application start-up into a sleep state. At time t0, 5VSB (bias)
is applied to the circuit. At time t1, the 5VSB surpasses POR
level. Time t2, one soft-start interval after t1, denotes the
4 FN7814.2
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ISL6506BI
initiation of soft-start. The 3.3VDUAL rail is brought up
through the internal standby LDO through an internal digital
soft-start function. Figure 3 shows the 5VDUAL rail initiating a
soft-start at time t2 as well.
At time t4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp-up. With the ISL6506BIBZ
(Figure 2), the 5VDUAL rail will begin to ramp-up from the
5VATX rail through the body diode of the N-MOSFET (Q3). At
time t5, the 12VATX rail has surpassed the 12V POR level.
Time t6 is three soft-start cycles after the 12V POR level has
been surpassed. At time t6, three events occur
simultaneously. The DLA pin is forced to a high impedance
state which allows the 12V rail to enhance the two N-
MOSFETs (Q1 and Q3) that connect the ATX rails to the
3.3VDUAL and 5VDUAL rails. The 5VDLSB pin is actively
pulled high, which will turn the P-MOSFET (Q2) off. Finally,
the internal LDO which regulates the 3.3VAUX rail in sleep
states is put in standby mode.
5VSB
(1V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
0V
DLA
(10V/DIV)
t0 t1 t2 t3
t4 t5
TIME
t6
FIGURE 2. ISL6506BIBZ SOFT-START INTERVAL IN S4/S5
STATE AND S5 TO S0 TRANSITION
Sleep to Wake State Transitions
Figures 2 and 3, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 2 shows the
transition of the ISL6506BIBZ from the S4/S5 state to the S0
state. Figure 3 shows how the ISL6506BIBZ will transition
from the S3 sleep state into S0 state. For all transitions, t4
depicts the system transition into the S0 state. Here, the ATX
supplies are enabled and begin to ramp up. At time t5, the
12VATX rail has exceeded the POR threshold. Three soft-
start periods after time t5, at time t6, three events occur
simultaneously. The DLA pin is forced to a high impedance
state, which allows the 12V rail to enhance the two N-
MOSFETs (Q1 and Q3) that connect the ATX rails to the
3.3VDUAL and 5VDUAL rails. The 5VDLSB pin is actively
pulled high, which will turn the P-MOSFET (Q2) off. Finally,
the internal LDO which regulates the 3.3VDUAL rail in sleep
states is put in standby mode.
5VSB
(1V/DIV)
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
0V
5VDLSB
(5V/DIV)
DLA
(10V/DIV)
t0 t1 t2 t3
t4 t5
TIME
t6
FIGURE 3. SOFT-START INTERVAL FOR S3 TO S0
TRANSITION FOR ISL6506BIBZ
Internal Linear Regulator Undervoltage Protection
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft-start
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft-start interval later, the 3.3V linear
regulator is retried with a soft-start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
Internal Linear Regulator Overcurrent Protection
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced, which
causes the output voltage of the linear regulator to be
reduced. When the output voltage is reduced to the
undervoltage trip point, the undervoltage protection is
initiated and the output will shutdown.
Layout Considerations
The typical application employing an ISL6506BIBZ is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
from the 3.3VDUAL island or the I/O circuitry. Ensure the
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5VSB) carries a similar level
of current (for best results, ensure it is connected to its
respective source through an adequately sized trace and is
5 FN7814.2
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