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®
Data Sheet
April 24, 2008
ISL6615
FN6481.0
High-Frequency 6A Sink Synchronous
MOSFET Drivers with Protection Features
The ISL6615 is a high-speed MOSFET driver optimized to
drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. This driver,
combined with an Intersil Digital or Analog multiphase PWM
controller, forms a complete high frequency and high
efficiency voltage regulator.
The ISL6615 drives both upper and lower gates over a range
of 4.5V to 13.2V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses.
The ISL6615 features 6A typical sink current for the low-side
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. The ISL6615 includes an overvoltage protection
feature operational before VCC exceeds its turn-on
threshold, at which the PHASE node is connected to the
gate of the low side MOSFET (LGATE). The output voltage
of the converter is then limited by the threshold of the low
side MOSFET, which provides some protection to the load if
the upper MOSFET(s) is shorted.
The ISL6615 also features an input that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevent negative transients
on the controlled output voltage when operation is
suspended. This feature eliminates the need for the Schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- LGATE Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 6A LGATE Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Support 3.3V PWM Input logic
• Tri-State PWM Input for Safe Output Stage Shutdown
• Tri-State PWM Input Hysteresis for Applications with
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper PAD for Better Heat
Spreading
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current Low-Profile DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• Synchronous Rectification for Isolated Power Supplies
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6615
Ordering Information
PART NUMBER
(Note)
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6615CBZ*
6615 CBZ
0 to +70
8 Ld SOIC
M8.15
ISL6615CRZ*
6615
0 to +70
10 Ld 3x3 DFN
L10.3x3
ISL6615IBZ*
6615 IBZ
-40 to +70
8 Ld SOIC
M8.15
ISL6615IRZ*
615I
-40 to +70
10 Ld 3x3 DFN
L10.3x3
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinouts
ISL6615
(8 LD SOIC)
TOP VIEW
ISL6615
(10 LD 3x3 DFN)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
8 PHASE
7 PVCC
6 VCC
5 LGATE
UGATE 1
BOOT 2
N/C 3
PWM 4
5
GND
GND
10 PHASE
9 PVCC
8 N/C
7 VCC
6 LGATE
RECOMMEND TO CONNECT PIN 3 TO GND AND PIN 8 TO PVCC
Block Diagram
ISL6615
VCC
PWM
(UVCC)
+5V PRE-POR OVP
FEATURES
13.6k
6.4k
POR/
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
(LVCC)
BOOT
UGATE
PHASE
PVCC
UVCC = PVCC
LGATE
GND
SUBSTRATE RESISTANCE
PAD
FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
2 FN6481.0
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Typical Application - 2 Channel Converter
+5V
PGOOD
VID
(OPTIONAL)
+5V
FB COMP
VCC
VSEN
PWM1
PWM2
PWM
CONTROL
(ISL63xx
OR ISL65xx)
ISEN1
ISEN2
FS/EN
GND
+7V TO +13.2V
PVCC
BOOT
VCC
PWM
UGATE
ISL6615
PHASE
LGATE
GND
VIN
+7V TO +13.2V
PVCC
BOOT
VCC
PWM
ISL6615
GND
UGATE
PHASE
LGATE
VIN
ISL6615 CAN SUPPORT 3.3V OR 5V PWM INPUT
+VCORE

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ISL6615
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND < 36V))
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 100
N/A
DFN Package (Notes 2, 3) . . . . . . . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range
ISL6615CRZ, ISL6615CBZ . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6615IRZ, ISL6615IBZ . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . +125°C
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
VCC Rising Threshold
IVCC
IPVCC
fPWM = 300kHz, VVCC = 12V
fPWM = 300kHz, VPVCC = 12V
- 4.5 - mA
- 8 - mA
6.1 6.4 6.7
V
VCC Falling Threshold
4.7 5.0 5.3
V
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current
IPWM
PWM Rising Threshold (Note 4)
VPWM = 3.3V
VPWM = 0V
VCC = 12V
- 365 -
- -350 -
- 1.70 -
µA
µA
V
PWM Falling Threshold (Note 4)
VCC = 12V
- 1.30 -
V
Typical Tri-State Shutdown Window
VCC = 12V
1.32 - 1.82 V
Tri-State Lower Gate Falling Threshold
VCC = 12V
- 1.18 -
V
Tri-State Lower Gate Rising Threshold
Tri-State Upper Gate Rising Threshold
VCC = 12V
VCC = 12V
- 0.76 -
- 2.36 -
V
V
Tri-State Upper Gate Falling Threshold
Shutdown Holdoff Time
UGATE Rise Time (Note 4)
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
tTSSHD
tRU
tRL
tFU
tFL
VCC = 12V
VPVCC = 12V, 3nF Load, 10% to 90%
VPVCC = 12V, 3nF Load, 10% to 90%
VPVCC = 12V, 3nF Load, 90% to 10%
VPVCC = 12V, 3nF Load, 90% to 10%
- 1.96 -
- 65 -
- 13 -
- 10 -
- 10 -
- 10 -
V
ns
ns
ns
ns
ns
4 FN6481.0
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ISL6615
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Tri-State Propagation Delay (Note 4)
OUTPUT (Note 4)
tPDHU
tPDHL
tPDLU
tPDLL
tPDTS
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
- 10 - ns
- 10 - ns
- 10 - ns
- 10 - ns
- 10 - ns
Upper Drive Source Current
IU_SOURCE VPVCC = 12V, 3nF Load
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
Upper Drive Sink Current
IU_SINK VPVCC = 12V, 3nF Load
Upper Drive Sink Impedance
RU_SINK 150mA Sink Current
Lower Drive Source Current
IL_SOURCE VPVCC = 12V, 3nF Load
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
Lower Drive Sink Current
IL_SINK VPVCC = 12V, 3nF Load
Lower Drive Sink Impedance
RL_SINK 150mA Sink Current
NOTE:
4. Limits established by characterization and are not production tested.
- 2.5 -
-1-
-4-
- 0.8 -
-4-
- 0.7 -
-6-
- 0.45 -
A
Ω
A
Ω
A
Ω
A
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the “TIMING
DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.
- 3, 8 N/C No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the “TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of
the controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
7 9 PVCC This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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