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Synchronous Rectified Buck MOSFET Drivers
ISL6625A
The ISL6625A is a high frequency MOSFET driver designed to
drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology.
In ISL6625A, the upper and lower gates are both driven to an
externally applied voltage. This provides the capability to
optimize applications involving trade-offs between gate charge
and conduction losses.
An advanced adaptive shoot-through protection is integrated to
prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize dead time. The ISL6625A has
a 10kintegrated high-side gate-to-source resistor to prevent
self turn-on due to high input bus dV/dt.
This driver also has an overvoltage protection feature, which is
operational while VCC is below the POR threshold. The PHASE
node is connected to the gate of the low-side MOSFET (LGATE)
via a 30kresistor, limiting the output voltage of the converter
close to the gate threshold of the low-side MOSFET. This is
dependent on the current being shunted, which provides some
protection to the load should the upper MOSFET(s) become
shorted.
Applications
• High light load efficiency voltage regulators
• Core regulators for advanced microprocessors
• High current DC/DC converters
Features
• Dual MOSFET drives for synchronous rectified bridge
• Advanced adaptive zero shoot-through protection
- PHASE detection
- LGATE detection
- Auto-Zero of rDS(ON) conduction offset effect
• Low standby bias current
• 36V internal bootstrap switcher
• Bootstrap capacitor overcharging prevention
• Integrated high-side gate-to-source resistor to prevent from
self turn-on due to high input bus dV/dt
• Pre-POR overvoltage protection for start-up and shutdown
• Power rails undervoltage protection
• Expandable bottom copper pad for enhanced heat sinking
• Dual flat no-lead (DFN) package
- Near chip-scale package footprint; improves PCB
efficiency and thinner in profile
• Pb-Free (RoHS compliant)
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck Regulators”
VCC
PIN 6
PWM
+5V
30.4k
POR/
CONTROL
LOGIC
32k
SHOOT-
THROUGH
PROTECTION
FIGURE 1. BLOCK DIAGRAM
BOOT
UGATE
10k
PHASE
30k
VCC
PIN 7
PINS 6 AND 7 MUST BE
TIED TOGETHER
LGATE
GND
September 19, 2012
FN7978.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL6625A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6625ACRZ-T
5AZ
0 to +70
8 Ld 2x2 DFN
L8.2x2D
ISL6625AIRZ-T
25A
-40 to +85
8 Ld 2x2 DFN
L8.2x2D
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6625A. For more information on MSL please see tech brief TB363
Pin Configuration
ISL6625A
(8 LD 2x2 DFN)
TOP VIEW
UGATE 1
BOOT 2
PWM 3
GND 4
GND
8 PHASE
7 VCC
6 VCC
5 LGATE
Functional Pin Descriptions
PIN
PIN # SYMBOL
FUNCTION
1 UGATE Upper gate drive output. Connect to gate of high-side
power N-Channel MOSFET.
2 BOOT Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin
and the PHASE pin. The bootstrap capacitor provides
the charge to turn on the upper MOSFET. See
“Internal Bootstrap Device” on page 6 for guidance in
choosing the capacitor value.
3 PWM The PWM signal is the control input for the driver. The
PWM signal can enter three distinct states during
operation, see the three-state PWM Input section for
further details. Connect this pin to the PWM output of
the controller.
4 GND Bias and reference ground. All signals are referenced
to this node. It is also the power ground return of the
driver.
5 LGATE Lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
6,7 VCC These two pins must tie to each other. Connect them
to 12V bias supply. Place a high quality low ESR
ceramic capacitor from this pin to GND.
8 PHASE Connect this pin to the SOURCE of the upper MOSFET
and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
- PAD Connect this pad to the power ground plane (GND) via
thermally enhanced connection.
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ISL6625A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
BOOT Voltage (VBOOT - GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VVCC + 0.3V
PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 25VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT - GND<36V)
ESD Rating
Human Body Model (Tested per Class I JEDEC STD) . . . . . . . . . . . .2.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250V
Thermal Information
Thermal Resistance
θJA (°C/W) θJC (°C/W)
2x2 DFN Package (Notes 4, 5) . . . . . . . . . .
90
25
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Ambient Temperature Range (ISL6625AIRZ). . . . . . . . . . . -40°C to +85°C
Ambient Temperature Range (ISL6625ACRZ) . . . . . . . . . . . .0°C to +70°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 13.2V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended operating conditions, unless otherwise noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
VCC SUPPLY CURRENT (Note 6)
No Load Switching Supply Current
POWER-ON RESET
IVCC VVCC = 12V, FPWM = 300kHz
IVCC VVCC = 12V, PWM = 2.5V
-
-
VCC Rising Threshold
-
VCC Falling Threshold
PWM INPUT (See “TIMING DIAGRAM” on page 4)
-
Input Current
Three-State Upper Gate Rising Threshold
IPWM
VPWM = 5V
VPWM = 0V
VCC = 12V
-
-
-
Three-State Upper Gate Falling Threshold
VCC = 12V
-
Three-State Lower Gate Rising Threshold
VCC = 12V
-
Three-State Lower Gate Falling Threshold
VCC = 12V
-
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
tRU
tRL
tFU
tFL
tPDHU
tPDHL
tPDLU
tPDLL
VVCC = 12V, 3nF Load, 10% to 90%
VVCC = 12V, 3nF Load, 10% to 90%
VVCC = 12V, 3nF Load, 90% to 10%
VVCC = 12V, 3nF Load, 90% to 10%
VVCC = 12V, 3nF Load, Adaptive
VVCC = 12V, 3nF Load, Adaptive
VVCC = 12V, 3nF Load
VVCC = 12V, 3nF Load
-
-
-
-
-
-
-
-
TYP
7.56
0.72
4.64
4.17
124
-141
2.77
3.23
1.20
1.50
31
28
18
16
16
38
21
23
MAX
(Note 6) UNITS
- mA
- mA
-V
-V
- µA
- µA
-V
-V
-V
-V
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
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ISL6625A
Electrical Specifications Recommended operating conditions, unless otherwise noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNITS
OUTPUT
Upper Drive Source Impedance
RU_SOURCE 20mA Source Current
- 3.9 -
Upper Drive Sink Impedance
RU_SINK 20mA Sink Current
- 1.4 -
Lower Drive Source Impedance
RL_SOURCE 20mA Source Current
- 2.7 -
Lower Drive Sink Impedance
RL_SINK 20mA Sink Current
- 0.9 -
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
PWM
tPDHU
UGATE
LGATE
tPDLL
tRU
tFL
tPDLFUR
1.5V<PWM<3.2V
tPDLU
tFU
tPDHL
tRL
tPDUFLR
tTSSHD
FIGURE 2. TIMING DIAGRAM
tPDTS
1.0V<PWM<2.6V
tUG_OFF_DB
tPDTS
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Typical Application Circuit
ISL6625A
+5V
VTT
SVALERT#
SVDATA
SVCLK
VR_RDY
VR_RDYS
VR_HOT#
VIN
FB COMP VCC PWM1
PSICOMP
HFCOMP
ISEN1-
ISEN1+
VSEN
RGND
EN_VTT
PWM2
ISEN2-
ISEN2+
ISL6364A
OVP
VIN
+5V
+5V
+5V
+5V
+5V
EN_PWR_OVP
RAMP_ADJ
PWM3
ISEN3-
ISEN3+
IMON
IMONS
FS_DRP
FSS_DRPS
BTS_DES_TCOMPS
PWM4
ISEN4-
ISEN4+
BT_FDVID_TCOMP
ADDR_IMAXS_TMAX
GND
NPSI_DE_IMAX
PWMS
ISENS-
+5V TMS
NTC
ISENS+
RGNDS
NTC
TM
AUTO
VSENS
HFCOMPS/DVCS
RSET COMPS FBS
+12V
BOOT
VCC
ISL6625A
PWM
UGATE
PHASE
GND
LGATE
+12V
BOOT
VCC
ISL6625A
PWM
UGATE
PHASE
GND
LGATE
VIN
VIN
+12V
BOOT
VCC
ISL6625A
PWM
UGATE
PHASE
GND
LGATE
+12V
BOOT
VCC
ISL6625A
PWM
UGATE
PHASE
GND
LGATE
+12V
BOOT
VCC
ISL6625A
PWM
UGATE
PHASE
GND
LGATE
VIN
VIN
VIN
NTC: Beta = ~ 3477
5
CPU
LOAD
GPU
LOAD
FN7978.0
September 19, 2012