(Notes 1, 2, 3)
TEMP. RANGE (°C)
-40 to +105
20 Ld QSOP
ISL6754 Evaluation Daughter Board
1. Add -T suffix for 2.5k unit tape and reel option. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6754. For more information on MSL, please see tech brief TB363.
VREF The 5.00V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a
0.1µF to 2.2µF low ESR capacitor.
The control voltage input to the inverting input of the PWM comparator. The output of an external Error Amplifier (EA) is applied
to this input, either directly or through an opto-coupler, for closed loop regulation. VERR has a nominal 1mA pull-up current
When VERR is driven by an opto-coupler or other current source device, a pull-up resistor from VREF is required to linearize the
gain. Generally, a pull-up resistor on the order of 5kΩ is acceptable.
CTBUF CTBUF is the buffered output of the sawtooth oscillator waveform present on CT and is capable of sourcing 2mA. It is offset
from ground by 0.40V and has a nominal valley-to-peak gain of 2. It may be used for slope compensation.
RTD This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this
pin and GND determines the magnitude of the current that discharges CT. The CT discharge current is nominally 20x the
resistor current. The PWM dead time is determined by the timing capacitor discharge duration. The voltage at RTD is nominally
Sets the resonant delay period between the toggle of the upper FETs and the turn on of either of the lower FETs. The voltage
applied to RESDEL determines when the upper FETs switch relative to a lower FET turning on. Varying the control voltage from
0V to 2.00V increases the resonant delay duration from 0 to 100% of the dead time. The control voltage divided by 2
represents the percent of the dead time equal to the resonant delay. In practice the maximum resonant delay must be set
lower than 2.00V to ensure that the lower FETs, at maximum duty cycle, are OFF prior to the switching of the upper FETs.
CT The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200µA current source
and discharged with a user adjustable current source controlled by RTD.
FB FB is the inverting inputs to the Error Amplifier (EA). The amplifier may be used as the error amplifier for voltage feedback or
used as the average current limit amplifier (IEA). If the amplifier is not used, FB should be grounded.
This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at the termination of
the PWM signal. A sawtooth voltage waveform is required at this input. For current-mode control this pin is connected to CS
and the current loop feedback signal is applied to both inputs. For voltage-mode control, the oscillator sawtooth waveform
may be buffered and used to generate an appropriate signal, RAMP may be connected to the input voltage through a RC
network for voltage feed forward control, or RAMP may be connected to VREF through a RC network to produce the desired
CS This is the input to the overcurrent comparator. The overcurrent comparator threshold is set at 1.00V nominal. The CS pin is
shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the
internal clock and the external power switch. This delay may result in CS being discharged prior to the power switching device
being turned off.
IOUT Output of the 4X buffer amplifier of the sample and hold circuitry that captures and averages the CS signal.
GND Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low
impedance layout is necessary. Ground planes and short traces are highly recommended.
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June 2, 2016