Functional Pin Descriptions
VCC (Pin 11)
Provide a well decoupled 5V bias supply for the IC to this
pin. This pin also provides the gate bias charge for the lower
MOSFET controlled by the PWM section of the IC, as well as
the drive current for the linear regulators. The voltage at this
pin is monitored for Power-On Reset (POR) purposes.
GND (Pin 5)
Signal ground for the controller. All voltage levels are
measured with respect to this pin.
PGND (Pin 9)
This is the power ground connection. Tie the source of the
lower MOSFET of the synchronous PWM converter to this
BOOT (Pin 7)
Floating bootstrap supply pin for the upper gate drive. The
bootstrap capacitor provides the necessary charge to turn
and hold the upper MOSFET on. Connect a suitable
capacitor (0.47F recommended) from this pin to PHASE.
OCSET (Pin 12)
Connect a resistor from this pin to the drain of the upper
PWM MOSFET. This resistor, an internal 40A current
source (typical), and the upper MOSFET’s on-resistance set
the converter overcurrent trip point. An overcurrent trip
cycles the soft-start function.
The voltage at this pin is monitored for power-on reset
(POR) purposes and pulling this pin below 1.25V with an
open drain/collector device will shut down the switching
PHASE (Pin 6)
Connect this pin to the source of the PWM converter upper
MOSFET. This pin is used to monitor the voltage drop across
the upper MOSFET for overcurrent protection.
UGATE (Pin 8)
Connect UGATE pin to the PWM converter’s upper
MOSFET gate. This pin provides the gate drive for the upper
LGATE (Pin 10)
This pin provides the gate drive for the synchronous rectifier
lower MOSFET. Connect LGATE to the gate of the lower
COMP and FB (Pins 4, 3)
COMP and FB are the available external pins of the PWM
converter error amplifier. The FB pin is the inverting input of the
error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM converter.
DRIVE2, 3, 4 (Pins 1, 15, 13)
Connect these pins to the point of load or to the base
terminals of external bipolar NPN transistors. These pins are
each capable of providing 120mA of load current or drive
current for the pass transistors.
FB2, 3, 4 (Pins 2, 16, 14)
Connect the output of the corresponding linear regulators to
these pins through properly sized resistor dividers. The
voltage at these pins is regulated to 0.8V. These pins are
also monitored for undervoltage events.
Quickly pulling and holding any of these pins above 1.25V
(using diode-coupled logic devices) shuts off the respective
regulators. Releasing these pins from the pull-up voltage
initiates a soft-start sequence on the respective regulator.
The ISL6521 monitors and precisely controls one
synchronous PWM converter and three configurable linear
regulators from a +5V bias input. The PWM controller is
designed to regulate the core voltage of an embedded
processor or simple down conversion for high current
applications. The PWM controller drives two MOSFETs (Q1
and Q2) in a synchronous-rectified buck converter
configuration and regulates the output voltage to a level
programmed by a resistor divider. The linear controllers are
designed to regulate three additional system voltages.
Typically, these include any I/O, memory, or clock voltages
that might be required. All three linear controllers support
up to 120mA of load current without external pass devices
or higher currents with external NPN bipolar transistors.
The ISL6521 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the input bias supply voltage. The POR monitors
the bias voltage at the VCC pin. The POR function initiates
soft-start operation after the bias supply voltage exceeds its
The POR function initiates the soft-start sequence. The
PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s).
Similarly, all linear regulators’ reference inputs are clamped
to a voltage proportional to the soft-start voltage. The ramp-
up of the internal soft-start function provides a controlled
output voltage rise.
Figure 1 shows the soft-start sequence for a typical
application. At T0 the +5V bias voltage starts to ramp up
crossing the 4.5V POR threshold at time T1. On the PWM
section, the oscillator’s triangular waveform is compared to