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DATASHEET
Dual PWM Controller For Powering AMD SVI Split-Plane
Processors
ISL6328A
The ISL6328A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6328A supports power control of AMD
processors, which operate from a serial VID interface (SVI). The
dual output ISL6328A features a multiphase controller to
support the Core voltage (VDD) and a single phase controller to
power the Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-four-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in
layout and reduces the number of external components in the
multiphase section. A single phase PWM controller with
integrated driver provides a second precision voltage
regulation system for the Northbridge portion of the processor.
This monolithic, dual controller with an integrated driver
solution provides a cost and space saving power management
solution.
For applications that benefit from load line programming to
reduce bulk output capacitors, the ISL6328A features
temperature compensated output voltage droop. The multiphase
portion also includes advanced control loop features for
optimal transient response to load application and removal.
One of these features is highly accurate, fully differential,
continuous DCR current sensing for load line programming
and channel current balance. Dual edge modulation is another
unique feature, allowing for quicker initial response to high
di/dt load transients.
The ISL6328A supports Power Savings Mode by dropping the
number of phases when the PSI_L bit is set.
Features
• Processor core voltage via integrated multiphase power
conversion
• Configuration flexibility
- 1 or 2-phase operation with internal drivers
- 3 or 4-phase operation with external PWM drivers
• PSI_L support
- Phase shedding for improved efficiency at light load
- Diode emulation in PSI mode
- Gate voltage optimization
• Precision core voltage regulation
- Differential remote voltage sensing
- ±0.6% system accuracy over-temperature
• Optimal processor core voltage transient response
- Adaptive phase alignment (APA)
- Active pulse positioning modulation
• Fully differential, continuous DCR current sensing
- Accurate load line programming
- Precision channel current balancing
- Temperature compensated
• Serial VID interface handles up to 3.4MHz clock rates
• Two level overcurrent protection allows for high current
throttling (IDD_SPIKE)
• Multitiered overvoltage protection
• Selectable switching frequency up to 1MHz
• Simultaneous digital soft-start of both outputs
February 13, 2015
FN7986.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL6328A
Table of Contents
Integrated Driver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 9
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Active Pulse Positioning Modulated PWM Operation . . . . . . 13
Adaptive Phase Alignment (APA) . . . . . . . . . . . . . . . . . . . . . . 13
PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Continuous Current Sampling . . . . . . . . . . . . . . . . . . . . . . . . . 14
Temperature Compensated Current Sensing. . . . . . . . . . . . . 15
Channel-current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial VID Interface (SVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pre-PWROK METAL VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SVI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Savings Mode: PSI_L . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Load-line (Droop) Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Droop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Voltage Offset Programming. . . . . . . . . . . . . . . . . . . . 19
Dynamic VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Advanced Adaptive Zero Shoot-through Deadtime Control
(Patent Pending) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Enable Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Phase Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Soft-start Output Voltage Targets . . . . . . . . . . . . . . . . . . . . . . 20
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Prebiased Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . 21
Power-good Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pre-POR Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . 21
Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Open Sense Line Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Individual Channel Overcurrent Limiting . . . . . . . . . . . . . . . . 23
General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Internal Bootstrap Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Gate Drive Voltage Versatility . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Inductor DCR Current Sensing Component Fine Tuning . . . 25
Loadline Regulation Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 26
Compensation With Loadline Regulation . . . . . . . . . . . . . . . 26
Compensation Without Loadline Regulation . . . . . . . . . . . . 26
Output Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Routing UGATE, LGATE, and PHASE Traces. . . . . . . . . . . . . . 30
Current Sense Component Placement and Trace Routing 30
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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ISL6328A
Integrated Driver Block Diagram
Channels 1 and 2 Gate Drive
GVOT
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
Northbridge Gate Drive
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PVCC
BOOTn
UGATEn
20kΩ
10kΩ
PHASEn
LGATEn
PVCC
BOOT_NB
UGATE_NB
20kΩ
10kΩ
PHASE_NB
LGATE_NB
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ISL6328A
Controller Block Diagram
VSEN_NB
ISEN_NB+
ISEN_NB-
DRPCTRL
VDDPWRGD
OFS
COMP
CSUERNRSEENT
DROOP
CONTROL
OFFSET
RGND
NB_REF
UV
LOGIC
OV
LOGIC
NB
FAULT
LOGIC
FB_NB
COMP_NB
E/A
RAMP
EN_12V
ENABLE
LOGIC
FB_PSI
FB
RGND
PWROK
SVC
SVD
VSEN
APA
OCP
CH3_OFF
PSI
+
RGND +
SVI
SLAVE
BUS
E/A
NB_REF
OV
LOGIC
APA
UV
LOGIC
OC
DUAL
OCP
I_TRIP
8
N
SOFT-START
AND
FAULT LOGIC
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
PWM1
PWM2
MOSFET
DRIVER
LDO
POWER-ON
RESET
MOSFET
DRIVER
MOSFET
DRIVER
TCOMP1
TCOMP2
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
TEMPERATURE
COMPENSATION
CSUECRNHRS1EENT
CSUECRNHRS2EENT
CSUECRNHRS3EENT
CUCRHR4ENT
SENSE
ISEN3-
ISEN4-
I_TC_IN
PWM3
PWM4
CHANNEL
CURRENT
BALANCE
I_AVG 1
N
I_TC_IN
1
8
GND
PH3/PH4
POR
CHANNEL
DETECT
EN_12V
ISEN2-
ISEN3-
ISEN4-
SLPIOGWGNMIAC3L
SPIGWNMA4L
LOGIC
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PVCC
EN
VCC
GVOT
BOOT1
UGATE1
PHASE1
LGATE1
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
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Typical Application
VCC
+5V
ISL6328A
CS1-
CS1+
CS2-
CS2+
CS3-
CS3+
CS4-
CS4+
CS_NB-
CS_NB+
+12V
ENABLE
CORE_FB
VCC RSVD
ISEN1-
TCOMP1
ISEN1+
TCOMP2
ISEN2-
ISEN2+
PWM3
PWM4
ISEN3-
ISEN3+
ISL6328A
PVCC
GVOT
ISEN4-
ISEN4+
BOOT1
ISEN_NB-
ISEN_NB+
UGATE1
PHASE1
LGATE1
DRPCTRL
FS
OFS
OCP
SVC
SVD
PWROK
VDDPWRGD
EN
APA
BOOT2
UGATE2
PHASE2
LGATE2
VSEN
RGND
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
FB_PSI
FB
COMP
VSEN_NB
FB_NB
COMP_NB
GND
PWM3
PWM4
+12V
+12V
+12V
CS1-
CS1+
+12V
+12V
CS3-
CS3+
CS2-
CS2+
CS4-
CS4+
ISL6614
BOOT1 PWM1
PWM3
PWM2
PWM4
UGATE1
PHASE1
+12V
LGATE1 PVCC
VCC
BOOT2
GND
UGATE2
PHASE2
PGND
LGATE2
CORE_FB
+12V
CS_NB-
CS_NB+
CORE
CPU
NORTHBRIDGE
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