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Dual PWM Controller Powering AMD SVI Split-Plane
Processors
ISL6329
The ISL6329 dual PWM controller delivers high efficiency and
tight regulation from two synchronous buck DC/DC converters.
The ISL6329 supports power control of AMD processors, which
operate from a serial VID interface (SVI). The dual output
ISL6329 features a multiphase controller to support the Core
voltage (VDD) and a single phase controller to power the
Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-six-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in layout
and reduces the number of external components in the
multi-phase section. A single phase PWM controller with
integrated driver provides a second precision voltage regulation
system for the Northbridge portion of the processor. This
monolithic, dual controller with integrated driver solution
provides a cost and space saving power management solution.
For applications that benefit from load line programming to reduce
bulk output capacitors, the ISL6329 features temperature
compensated output voltage droop. The multiphase portion also
includes advanced control loop features for optimal transient
response to load application and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current balance.
Dual edge modulation is another unique feature, allowing for
quicker initial response to high di/dt load transients.
The ISL6329 supports Power Savings Mode by dropping the
number of phases to one or two when the PSI_L bit is set. For
even greater power efficiency, diode emulation and gate voltage
optimization are implemented in PSI mode.
Features
• Processor Core Voltage Via Integrated Multiphase Power
Conversion
• Configuration Flexibility
- 1 or 2-Phase Operation with Internal Drivers
- 3,4,5 or 6-Phase Operation with External PWM Drivers
• PSI_L Support
- Phase Shedding for Improved Efficiency at Light Load
- Diode Emulation in PSI mode
- Gate Voltage Optimization
• I2C Interface with 8 Selectable Addresses
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
- Temperature Compensated
• Serial VID Interface Handles up to 3.4MHz Clock Rates
• Two Level Overcurrent Protection Allows for High Current
Throttling (IDD_SPIKE)
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Pb-Free (RoHS Compliant)
April 19, 2011
FN7800.0
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL6329
Integrated Driver Block Diagram
Channels 1 and 2 Gate Drive
GVOT
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
Northbridge Gate Drive
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PVCC
BOOT
UGATE
20k
10k
PHASE
LGATE
PVCC
BOOT
UGATE
20k
10k
PHASE
LGATE
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ISL6329
Controller Block Diagram
FB_NB
COMP_NB
VSEN_NB
ISEN_NB+
ISEN_NB-
I2C_ADDR
SCL
SDA
VDDPWRGD
OFS
COMP
FB_PSI
FB
RGND
PWROK
VDDIO
SVC
SVD
VSEN
APA
OCP
TCOMP1
TCOMP2
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
ISEN5+
ISEN5-
ISEN6+
ISEN6-
CURRENT
SENSE
I2C
DAC_OFS
NB_OVP
CORE_OVP
VDDPWRGD_TRIP
GVOT_LDO
NUM_PHASES_PSI
NUM_CYCLES_PSI
OFFSET
RGND
NB_REF
UV
LOGIC
OV
LOGIC
NB
FAULT
LOGIC
CH3_OFF
PSI
+
RGND
+
SVI
SLAVE
BUS
E/A
NB_REF
APA
OV
LOGIC
UV
LOGIC
OC
DUAL
OCP
I_TRIP
8
N
SOFT-START
AND
FAULT LOGIC
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
E/A
RAMP
MOSFET
DRIVER
EN_12V
ENABLE
LOGIC
LDO
POWER-ON
RESET
DROOP
CONTROL
MOSFET
DRIVER
PWM1
PWM2
PWM3
MOSFET
DRIVER
TEMPERATURE
COMPENSATION
CH1 CURRENT
SENSE
CH2 CURRENT
SENSE
CH3 CURRENT
SENSE
CH4 CURRENT
SENSE
CH5 CURRENT
SENSE
CH6 CURRENT
SENSE
ISEN2-
ISEN3-
ISEN4-
ISEN5-
ISEN6-
I_TC_IN
PWM4
PWM5
I_AVG
CHANNEL
CURRENT
BALANCE
PWM6
1
N
I_TC_IN
1
8
EN_12V
PH3/PH4/PH5/PH6
POR
CHANNEL
DETECT
ISEN2-
ISEN3-
ISEN4-
ISEN5-
ISEN6-
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
PWM5
SIGNAL
LOGIC
PWM6
SIGNAL
LOGIC
GND
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PVCC
EN
VCC
GVOT
BOOT1
UGATE1
PHASE1
LGATE1
DRPCTRL
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
PWM5
PWM6
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Typical Application
VCC
+5V
ISL6329
CS1-
CS1+
CS2-
CS2+
CS3-
CS3+
CS4-
CS4+
CS5-
CS5+
CS6-
CS6+
CS_NB-
CS_NB+
+12V
ENABLE
CORE_FB
ISEN1- VCC RSVD TCOMP1
ISEN1+
TCOMP2
ISEN2-
ISEN2+
ISEN3-
ISEN3+
ISEN4-
ISEN4+
ISL6329
PWM3
PWM4
PWM5
PWM6
PVCC
GVOT
BOOT1
ISEN5-
ISEN5+
UGATE1
PHASE1
ISEN6-
ISEN6+
ISEN_NB-
ISEN_NB+
LGATE1
BOOT2
UGATE2
PHASE2
I2C_ADDR
FS
OFS
OCP
VDDIO
SVC
SVD
SCL
SDA
PWROK
VDDPWRGD
EN
APA
DRPCTRL
LGATE2
VSEN
RGND
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
VSEN_NB
FB_NB
COMP_NB
FB_PSI
FB
COMP
GND
PWM3
PWM4
PWM5
PWM6
+12V
+12V
CS1-
CS1+
+12V
CS2-
CS2+
CORE_FB
+12V
CS_NB-
CS_NB+
+12V
CS3-
CS3+
+12V
CS4-
CS4+
+12V
CS5-
CS5+
+12V
CS6-
CS6+
CORE
CPU
NORTHBRIDGE
ISL6614
BOOT1 PWM1
PWM2
UGATE1
PHASE1
PWM3
PWM4
+12V
LGATE1 PVCC
VCC
BOOT2
GND
UGATE2
PHASE2
PGND
LGATE2
ISL6614
BOOT1 PWM1
PWM2
UGATE1
PHASE1
PWM5
PWM6
+12V
LGATE1 PVCC
VCC
BOOT2
GND
UGATE2
PHASE2
PGND
LGATE2
KELVIN
SENSE
LINES
KELVIN
SENSE
LINE
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Pin Configuration
ISL6329
ISL6329
(60 LD QFN)
TOP VIEW
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46
COMP_NB 1
FB_NB 2
VSEN_NB 3
DRPCTRL 4
SVC 5
SVD 6
VDDIO 7
SCL 8
SDA 9
VCC 10
RSVD 11
OFS 12
61
GND
45 PWM4
44 PWM5
43 PWM6
42 PWROK
41 VDDPWRGD
40 PHASE1
39 UGATE1
38 BOOT1
37 LGATE1
36 GVOT
35 LGATE2
34 BOOT2
OCP 13
TCOMP1 14
TCOMP2 15
33 UGATE2
32 GND
31 EN
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Functional Pin Descriptions
PIN NAME
COMP_NB
FB_NB
VSEN_NB
DRPCTRL
SVC
SVD
VDDIO
SCL
PIN NUMBER
1
2
3
4
5
6
7
8
DESCRIPTION
Output of the internal error amplifier for the Northbridge regulator.
Inverting input to the internal error amplifier for the Northbridge regulator.
Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor tied to ground: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop
On, Core Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
Serial VID clock input from the AMD processor.
Serial VID data bi-directional signal to and from the master device on AMD processor.
Reference voltage for the SVI communication bus. Connect this pin to the system VDDIO and decouple
using a quality 0.1μF ceramic capacitor.
Connect this pin to the clock signal for the I2C bus, which is a logic level input signal. The clock signal
tells the controller when data is available on the I2C bus.
5 FN7800.0
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