CAT28C65B.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 CAT28C65B 데이타시트 다운로드

No Preview Available !

CAT28C65B
64K-Bit CMOS PARALLEL E2PROM
FEATURES
s Fast Read Access Times:
– 120/150ns
s Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 100 µA Max.
s Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
– 5ms Max
s CMOS and TTL Compatible I/O
s Hardware and Software Write Protection
s Commercial, Industrial and Automotive
Temperature Ranges
s Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
s End of Write Detection:
– Toggle Bit
DATA Polling
– RDY/BUSY
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
DESCRIPTION
The CAT28C65B is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling, a RDY/BUSY pin and Toggle status bits
signal the start and end of the self-timed write cycle.
Additionally, the CAT28C65B features hardware and
software write protection.
The CAT28C65B is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC-
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5–A12
VCC
CE
OE
WE
A0–A4
RDY/BUSY
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING,
TOGGLE BIT &
RDY/BUSY LOGIC
COLUMN
DECODER
1
8,192 x 8
E2PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
5099 FHD F02
Doc. No. 25036-00 2/98 P-1

No Preview Available !

CAT28C65B
PIN CONFIGURATION
DIP Package (P)
RDY/BUSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC Package (N)
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
TOP VIEW
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
SOIC Package (J, K)
RDY/BUSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
TSOP Package (8mm x 13.4mm) (T13)
OE
A11
A9
A8
NC
WE
VCC
RDY/BUSY
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 CE
26 I/O7
25 I/O6
24 I/O5
23 I/O4
22 I/O3
21 GND
20 I/O2
19 I/O1
18 I/O0
17 A0
16 A1
15 A2
28C65B F03
PIN FUNCTIONS
Pin Name
Function
A0–A12
Address Inputs
I/O0–I/O7
CE
Data Inputs/Outputs
Chip Enable
OE Output Enable
RDY/BSY
Ready/Busy Status
Pin Name
WE
VCC
VSS
NC
Function
Write Enable
5 V Supply
Ground
No Connect
Doc. No. 25036-00 2/98 P-1
2

No Preview Available !

CAT28C65B
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
105
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
MODE SELECTION
Mode
CE WE OE I/O Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H DIN ACTIVE
Byte Write (CE Controlled)
L H DIN ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE TA = 25°C, F = 1.0 MHZ, VCC = 5V
Symbol
Test
Max.
CI/O(1) Input/Output Capacitance
10
CIN(1) Input Capacitance
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
3 Doc. No. 25036-00 2/98

No Preview Available !

CAT28C65B
D.C. OPERATING CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Symbol
ICC
ICCC(1)
ISB
ISBC(2)
ILI
ILO
VIH(2)
VIL(1)
VOH
VOL
VWI
Parameter
VCC Current (Operating, TTL)
VCC Current (Operating, CMOS)
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
Limits
Min. Typ.
Max.
30
Units
mA
25 mA
1 mA
100 µA
–10 10 µA
–10 10 µA
2 VCC +0.3 V
–0.3 0.8 V
2.4 V
0.4 V
3.5 V
Test Conditions
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
CE = OE = VILC,
f = 1/tRC min, All I/O’s Open
CE = VIH, All I/O’s Open
CE = VIHC,
All I/O’s Open
VIN = GND to VCC
VOUT = GND to VCC,
CE = VIH
IOH = –400µA
IOL = 2.1mA
Note:
(1) VILC = –0.3V to +0.3V.
(2) VIHC = VCC –0.3V to VCC +0.3V.
Doc. No. 25036-00 2/98 P-1
4

No Preview Available !

CAT28C65B
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V ±10%, unless otherwise specified.
Symbol
tRC
tCE
tAA
tOE
tLZ(1)
tOLZ(1)
tHZ(1)(2)
tOHZ(1)(2)
tOH(1)
Parameter
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
28C65B-12
Min. Max.
120
120
120
60
0
0
50
50
0
28C65B-15
Min. Max.
150
150
150
70
0
0
50
50
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1. A.C. Testing Input/Output Waveform(3)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
5096 FHD F03
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
5096 FHD F04
5 Doc. No. 25036-00 2/98