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CAT28F001
1 Megabit CMOS Boot Block Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 70/90/120/150 ns
s On-Chip Address and Data Latches
s Blocked Architecture
— One 8 KB Boot Block w/ Lock Out
• Top or Bottom Locations
— Two 4 KB Parameter Blocks
— One 112 KB Main Block
s Low Power CMOS Operation
s 12.0V ± 5% Programming and Erase Voltage
s Automated Program & Erase Algorithms
s High Speed Programming
s Commercial, Industrial and Automotive
Temperature Ranges
s Deep Powerdown Mode
— 0.05 µA ICC Typical
— 0.8 µA IPP Typical
s Hardware Data Protection
s Electronic Signature
s 100,000 Program/Erase Cycles and 10 Year
Data Retention
s JEDEC Standard Pinouts:
— 32 pin DIP
— 32 pin PLCC
— 32 pin TSOP
s Reset/Deep Power Down Mode
DESCRIPTION
The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram-
ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca-
tions of CAT28F001.
The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms.
The CAT28F001 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.
BLOCK DIAGRAM
WRITE STATE
MACHINE
RP
WE COMMAND
REGISTER
ADDRESS
COUNTER
ERASE VOLTAGE
SWITCH
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
I/O0–I/O7
I/O BUFFERS
DATA
LATCH
STATUS
REGISTER
SENSE
AMP
CE
OE
A0–A16
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Y-DECODER
X-DECODER
1
Y-GATING
8K-BYTE BOOT BLOCK
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK
112K-BYTE MAIN BLOCK
28F001 F01
Doc. No. 25071-00 2/98 F-1

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CAT28F001
PIN CONFIGURATION
DIP Package (P)
PLCC Package (N)
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
RP
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
4 3 2 1 32 31 30
A7 5
29 A14
A6 6
28 A13
A5 7
27 A8
A4 8
26 A9
A3 9
25 A11
A2 10
24 OE
A1 11
23 A10
A0 12
228F2001 F02CE
I/O0 13
21 I/O7
14 15 16 17 18 19 20
A11
A9
A8
A13
A14
RP
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP Package (Standard Pinout) (T)
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 VSS
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
PIN FUNCTIONS
Pin Name Type
A0–A16
Input
I/O0–I/O7
CE
OE
WE
VCC
VSS
VPP
I/O
Input
Input
Input
RP Input
Function
Address Inputs for
memory addressing
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Program/Erase
Voltage Supply
Power Down
Doc. No. 25071-00 2/98 F-1
2
28F001 F03

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CAT28F001
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
(Except A9, RP, OE, VCC and VPP)
Voltage on Pin A9, RP AND OE with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100K
10
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
CIN(3)
COUT(3)
CVPP(3)
Test
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
Limits
Min Max.
8
12
25
Units
pF
pF
pF
Conditions
VIN = 0V
VOUT = 0V
VPP = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
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CAT28F001
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified
Symbol
ILI
Parameter
Input Leakage Current
Min.
Limits
Max.
±1.0
Unit
µA
ILO Output Leakage Current
±10 µA
ISB1 VCC Standby Current CMOS
100 µA
ISB2 VCC Standby Current TTL
IPPD VPP Deep Powerdown Current
ICC1 VCC Active Read Current
1.5 mA
1.0 µA
30 mA
ICC2(1) VCC Programming Current
20 mA
ICC3(1) VCC Erase Current
20 mA
IPPS VPP Standby Current
IPP1
IPP2(1)
VPP Read Current
VPP Programming Current
±10 µA
200 µA
200 µA
30 mA
IPP3(1) VPP Erase Current
30 mA
VIL Input Low Level
–0.5 0.8 V
VOL Output Low Level
0.45 V
VIH Input High Level
2.0
VCC+0.5
V
VOH Output High Level
2.4 V
VID A9 Signature Voltage
11.5 13.0 V
IID A9 Signature Current
500 µA
ICCD
VCC Deep Powerdown Current
1.0 µA
ICCES VCC Erase Suspend Current
10 mA
IPPES VPP Erase Suspend Current
300 µA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Test Conditions
VIN = VCC or VSS
VCC = 5.5V
VOUT = VCC or VSS,
VCC = 5.5V
CE = VCC ±0.2V = RP
VCC = 5.5V
CE = RP = VIH, VCC = 5.5V
RP = GND±0.2V
VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 8 MHz
VCC = 5.5V,
Programming in Progress
VCC = 5.5V,
Erase in Progress
VPP < VCC
VPP > VCC
VPP = VPPH
VPP = VPPH,
Programming in Progress
VPP = VPPH,
Erase in Progress
IOL = 5.8mA, VCC = 4.5V
IOH = 2.5mA, VCC = 4.5V
A9 = VID
A9 = VID
RP = GND±0.2V
Erase Suspended CE = VIH
Erase Suspended VPP=VPPH
Doc. No. 25071-00 2/98 F-1
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CAT28F001
SUPPLY CHARACTERISTICS
Symbol
Parameter
Limits
Min Max.
Unit
VLKO
VCC Erase/Write Lock Voltage
2.5
V
VCC VCC Supply Voltage
4.5 5.5
V
VPPL
VPP During Read Operations
0 6.5 V
VPPH
VPP During Erase/Program
11.4 12.6
V
VHH RP, OE Unlock Voltage
11.4 12.6
V
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified
JEDEC Standard
Symbol Symbol
Parameter
tAVAV
tRC Read Cycle Time
28F001-70(8) 28F001-90(7)
Min. Max. Min. Max.
70 90
28F001-12(7) 28F001-15(7)
Min. Max. Min. Max. Unit
120 150
ns
tELQV
tAVQV
tGLQV
tCE CE Access Time
tACC Address Access Time
tOE OE Access Time
70 90
70 90
27 35
120 150 ns
120 150 ns
50 55 ns
-
tGLQX
tELQX
tGHQZ
tEHQZ
tOH Output Hold from Address OE/CE Change 0
0
0
0 ns
tOLZ(1)(6) OE to Output in Low-Z
0 0 0 0 ns
tLZ(1)(6)
CE to Output in Low-Z
0 0 0 0 ns
tDF(1)(2) OE High to Output High-Z
30 30 30 30 ns
tHZ(1)(2) CE High to Output High-Z
55 35 55 55 ns
tPHQV
tPWH
RP High to Output Delay
600 600 600 600 ns
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Testing Load Circuit (example)
5108 FHD F03
1.3V
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
3.0 V
0.0 V
INPUT PULSE LEVELS
1.5 V
REFERENCE POINTS
Testing Load Circuit (example)
5108 FHD F03A
1.3V
1N914
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
DEVICE
UNDER
TEST
3.3K
CL = 30 pF
OUT
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2
5108 FHD F05
5 Doc. No. 25071-00 2/98 F-1