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CAT28F010
1 Megabit CMOS Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 70/90/120 ns
s Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
s High Speed Programming:
–10 µs per byte
–2 Sec Typ Chip Program
s 0.5 Seconds Typical Chip-Erase
s 12.0V ± 5% Programming and Erase Voltage
s Stop Timer for Program/Erase
s Commercial, Industrial and Automotive
Temperature Ranges
s On-Chip Address and Data Latches
s JEDEC Standard Pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP (8 x 20)
s 100,000 Program/Erase Cycles
s 10 Year Data Retention
s Electronic Signature
DESCRIPTION
The CAT28F010 is a high speed 128K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
BLOCK DIAGRAM
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F010 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
I/O0–I/O7
ERASE VOLTAGE
SWITCH
I/O BUFFERS
WE
CE
OE
A0–A16
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
VOLTAGE VERIFY
SWITCH
Y-DECODER
X-DECODER
Y-GATING
1,048,576 BIT
MEMORY
ARRAY
5108 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25005-0A 2/98 F-1

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CAT28F010
PIN CONFIGURATION
DIP Package (P)
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
N/C
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
PLCC Package (N)
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
PIN FUNCTIONS
Pin Name Type
A0–A16
Input
I/O0–I/O7
CE
OE
WE
VCC
VSS
VPP
I/O
Input
Input
Input
Function
Address Inputs for
memory addressing
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Program/Erase
Voltage Supply
A11
A9
A8
A13
A14
NC
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
5108 FHD F01
5108 FHD F01
TSOP Package (Standard Pinout 8mm x 20mm) (T)
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP Package (Reverse Pinout) (TR)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
5108 FHD F14
Doc. No. 25005-0A 2/98 F-1
2

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CAT28F010
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100K
10
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
CIN(3)
COUT(3)
CVPP(3)
Test
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
Limits
Min Max.
6
10
25
Units
pF
pF
pF
Conditions
VIN = 0V
VOUT = 0V
VPP = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
3 Doc. No. 25005-0A 2/98 F-1

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CAT28F010
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified.
Symbol
ILI
Parameter
Input Leakage Current
Min.
Limits
Max.
±1
Unit
µA
ILO Output Leakage Current
±1 µA
ISB1 VCC Standby Current CMOS
100 µA
ISB2 VCC Standby Current TTL
ICC1 VCC Active Read Current
1 mA
30 mA
ICC2(1) VCC Programming Current
15 mA
ICC3(1) VCC Erase Current
15 mA
ICC4(1) VCC Prog./Erase Verify Current
15 mA
IPPS
IPP1
IPP2(1)
VPP Standby Current
VPP Read Current
VPP Programming Current
±10 µA
200 µA
30 mA
IPP3(1) VPP Erase Current
30 mA
IPP4(1) VPP Prog./Erase Verify Current
5 mA
VIL Input Low Level TTL
–0.5 0.8 V
VILC Input Low Level CMOS
–0.5 0.8 V
VOL Output Low Level
0.45 V
VIH Input High Level TTL
2
VCC+0.5
V
VIHC
Input High Level CMOS
VCC*0.7 VCC+0.5
V
VOH1 Output High Level TTL
2.4
V
VOH2 Output High Level CMOS
VCC–0.4
V
VID A9 Signature Voltage
11.4 13 V
IID(1)
A9 Signature Current
200 µA
VLO VCC Erase/Prog. Lockout Voltage 2.5
V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Test Conditions
VIN = VCC or VSS
VCC = 5.5V, OE = VIH
VOUT = VCC or VSS,
VCC = 5.5V, OE = VIH
CE = VCC ±0.5V,
VCC = 5.5V
CE = VIH, VCC = 5.5V
VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 6 MHz
VCC = 5.5V,
Programming in Progress
VCC = 5.5V,
Erasure in Progress
VCC = 5.5V, Program or
Erase Verify in Progress
VPP = VPPL
VPP = VPPH
VPP = VPPH,
Programming in Progress
VPP = VPPH,
Erasure in Progress
VPP = VPPH, Program or
Erase Verify in Progress
IOL = 5.8mA, VCC = 4.5V
IOH = –2.5mA, VCC = 4.5V
IOH = –400µA, VCC = 4.5V
A9 = VID
A9 = VID
Doc. No. 25005-0A 2/98 F-1
4

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CAT28F010
SUPPLY CHARACTERISTICS
Symbol
VCC
VPPL
VPPH
Parameter
VCC Supply Voltage
VPP During Read Operations
VPP During Read/Erase/Program
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified.
Limits
Min Max.
4.5 5.5
0 6.5
11.4 12.6
Unit
V
V
V
JEDEC Standard
Symbol Symbol Parameter
tAVAV
tELQV
tAVQV
tGLQV
tAXQX
tRC
tCE
tACC
tOE
tOH
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
Output Hold from Address
OE/CE Change
tGLQX tOLZ(1)(6)
tELZX
tLZ(1)(6)
tGHQZ tDF(1)(2)
tEHQZ tDF(1)(2)
tWHGL(1)
-
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
Write Recovery Time
Before Read
28F010-70(8)
Min. Max.
70
70
70
28
0
0
0
20
30
6
28F010-90(7) 28F010-12(7)
Min. Max. Min. Max.
90 120
90 120
90 120
35 50
00
00
00
20 30
30 40
66
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Testing Load Circuit (example)
5108 FHD F03
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
3.0 V
0.0 V
INPUT PULSE LEVELS
1.5 V
REFERENCE POINTS
Testing Load Circuit (example)
5108 FHD F03A
1.3V
1N914
1.3V
1N914
3.3K
3.3K
DEVICE
UNDER
TEST
Note:
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
DEVICE
UNDER
TEST
CL = 30 pF
OUT
CL INCLUDES JIG CAPACITANCE
5108 FHD F05
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2
5 Doc. No. 25005-0A 2/98 F-1