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CAT28LV64
64K-Bit CMOS PARALLEL EEPROM
FEATURES
3.0V to 3.6 V Supply
Read access times:
– 150/200/250ns
Low power CMOS dissipation:
– Active: 8 mA max.
– Standby: 100 µA max.
Simple write operation:
– On-chip address and data latches
– Self-timed write cycle with auto-clear
Fast write cycle time:
– 5ms max.
Commercial, industrial and automotive
temperature ranges
ALOGEN FR
LEA D F REETM
CMOS and TTL compatible I/O
Automatic page write operation:
– 1 to 32 bytes in 5ms
– Page load timer
End of write detection:
– Toggle bit
DATA polling
Hardware and software write protection
100,000 program/erase cycles
100 year data retention
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bit signal the start and end of the self-
timed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
The CAT28LV64 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
VCC
CE
OE
WE
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
A0–A4
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
8,192 x 8
E2PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1010, Rev. D

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CAT28LV64
PIN CONFIGURATION
DIP Package (P, L)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC Package (N, G)
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
TOP VIEW
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13 21
14 15 16 17 18 19 20
I/O6
SOIC Package (J, W) (K, X)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
TSOP Top View (8mm x 13.4mm) (T13, H13)
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 CE
26 I/O7
25 I/O6
24 I/O5
23 I/O4
22 I/O3
21 GND
20 I/O2
19 I/O1
18 I/O0
17 A0
16 A1
15 A2
PIN FUNCTIONS
Pin Name
Function
A0–A12
Address Inputs
I/O0–I/O7
CE
Data Inputs/Outputs
Chip Enable
OE Output Enable
Pin Name
WE
VCC
VSS
NC
Function
Write Enable
3.0 to 3.6 V Supply
Ground
No Connect
Doc. No. 1010, Rev. D
2

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CAT28LV64
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
105
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
MODE SELECTION
Mode
CE WE OE I/O Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H DIN ACTIVE
Byte Write (CE Controlled)
L H DIN ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
Test
CI/O(1)
Input/Output Capacitance
CIN(1)
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
3 Doc. No. 1010, Rev. D

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CAT28LV64
D.C. OPERATING CHARACTERISTICS
Vcc = 3.0V to 3.6V, unless otherwise specified.
Symbol
ICC
ISBC(3)
ILI
ILO
VIH(3)
VIL
VOH
VOL
VWI
Parameter
VCC Current (Operating, TTL)
VCC Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
Limits
Min. Typ.
Max.
8
Units
mA
100 µA
–1 1 µA
–5 5 µA
2
–0.3
2
2
VCC +0.3
0.6
0.3
V
V
V
V
V
Test Conditions
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
CE = VIHC,
All I/O’s Open
VIN = GND to VCC
VOUT = GND to VCC,
CE = VIH
IOH = –100µA
IOL = 1.0mA
A.C. CHARACTERISTICS, Read Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
Symbol
tRC
tCE
tAA
tOE
tLZ(1)
tOLZ(1)
tHZ(1)(2)
tOHZ(1)(2)
tOH(1)
Parameter
Read Cycle Time
CE Access Time
Address Access Time
OEAccess Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from
Address Change
28LV64-15
Min. Max.
150
150
150
70
0
0
50
50
28LV64-20
28LV64-25
Min. Max. Min. Max.
200 250
200 250
200 250
80 100
00
00
50 55
50 55
Units
ns
ns
ns
ns
ns
ns
ns
ns
0 0 0 ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) VIHC = VCC –0.3V to VCC +0.3V.
Doc. No. 1010, Rev. D
4

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Figure 1. A.C. Testing Input/Output Waveform(4)
VCC - 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
DEVICE
UNDER
TEST
1. 3K
1.8 K
OUTPUT
CL= 100 pF
CAT28LV64
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(2)
tOES
tOEH
tWP(2)
tDS
tDH
tINIT(1)
tBLC(1)(3)
Parameter
Write Cycle Time
Address Setup Time0
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period
After Power-up
Byte Load Cycle Time
28LV64-15
Min Max
5
0
100
0
0
110
0
0
110
60
0
5 10
0.05 100
28LV64-20
Min Max
5
0
100
0
0
150
10
10
150
100
0
28LV64-25
Min Max
5
0
100
0
0
150
10
10
150
100
0
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 10 5 10 ms
0.1 100 0.1 100 µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
5 Doc. No. 1010, Rev. D