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MITSMUIBTSISUHBI ISLHSIsLSIs
M5M4V4405MC5JM,4TVP44-065,C-J7,T,-P6-6S,-7,,--76SS,-7S
EDOE(DHOYP(HEYRPPEARGPEAMGOEDMEO) D41E9)44310944-3B0I4T-B(1I0T4(180547865-W76O-WRDORBDY B4-YB4IT-B) DITY)NDAYMNIACMRICAMRAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMS,
fabricated with the high performance CMOS process,and is ideal
for large-capacity memory systems where high speed, low power
dissipation , and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery
back-up application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
FEATURES
Type name
RAS CAS Address OE
access access access access
time time time time
Cycle
Power
dissipa-
time tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M4V4405CXX-6, -6S 60 15 30 15 110 264
M5M4V4405CXX-7, -7S 70 20 35 20 130 231
XX=J, TP
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 3.3V±0.3V supply
Low stand-by power dissipation
CMOS lnput level .................................................1.8mW(Max)*
CMOS lnput level ................................................180µW(Max)
Low operating power dissipation
M5M4V4405Cxx-6, -6S .....................................288.0mW (Max)
M5M4V4405Cxx-7, -7S ....................................252.0mW (Max)
Self refresh capabiility*
Self refresh current ..............................................100µA(max)
Extended refresh capability*
Extended refresh current ....................................100µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-6S,-7S) capabilities.
Early-write mode and OE and W to control output buffer impedance
1024 refresh cycles every 16.4ms (A0~A9)
1024refresh cycle every128ms (A0~A9)*
*: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S:
option) only
APPLICATION
Lap top personal computer,Solid state disc, Microcomputer
memory, Refresh memory for CRT
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P0J (300mil SOJ)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P3Z-E (300mil TSOP)
PIN DESCRIPTION
Pin name
A0~A9
DQ1~DQ4
RAS
CAS
W
OE
VCC
VSS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
1

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MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
FUNCTION
In addition to normal read, write, and read-modify-write operations
the M5M4V4405CJ,TP provide, a number of other functions, e.g.,
Hyper Page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS CAS
Inputs
W OE
Row Column
address address
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Self refresh*
Stand-by
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
NAC
ACT
ACT
ACT
DNC
DNC
NAC
NAC
DNC
ACT
DNC
NAC
ACT
DNC
ACT
DNC
DNC
DNC
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
APD
APD
AP
ADPD
DNC
DNC
DNC
DNC
DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
Input/Output
Refresh Remark
Input Output
OPN
APD
APD
APD
DNC
OPN
DNC
DNC
DNC
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
YES
YES
YES
YES
YES
YES
YES
YES
NO
Hyper
Page
mode
identical
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT CAS
ROW ADDRESS RAS
STROBE INPUT
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CLOCK GENERATOR
CIRCUIT
A0 ~ A9
COLUMN DECODER
ROW &
COLUMN
ADDRESS
BUFFER
A0~ ROW
A9 DECODER
SENSE REFRESH
AMPLIFER & I /O CONTROL
MEMORY CELL
(4,194,304 BITS)
(4)
DATA IN
BUFFERS
(4)
DATA OUT
BUFFERS
2
VCC (3.3V)
VSS (0V)
DQ1
DQ2
DQ3
DQ4
DATA
INPUTS /
OUTPUTS
OUTPUT
OE ENABLE
INPUT

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MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
VO
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to VSS
Ta=25 C
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
1000
0 ~ 70
-65 ~ 150
Unit
V
V
V
mA
mW
C
C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)
Symbol
Parameter
VCC Supply voltage
VSS Supply voltage
VIH High-level input voltage, all inputs
DQ1~DQ4
VIL
Low-level input voltage
others
Note 1 : All voltage values are with respect to VSS.
Limits
Min Nom Max
Unit
3.0 3.3 3.6
V
000V
2.0
VCC+0.3
V
-0.3 0.8 V
-0.3 0.8 V
ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V± 0.3V, VsS=0V, unless otherwise noted) (Note 2)
Symbol
VOH
VOL
IOZ
II
ICC1 (AV)
ICC2 (AV)
ICC3 (AV)
ICC4(AV)
ICC6(AV)
ICC8(AV)*
ICC9(AV)*
Parameter
Test conditions
High-level output voltage
Low-level output voltage
Off-state output current
IOH=-2mA
IOL=2mA
Q floating, 0VVOUTVCC
Input current
0VVINVCC+0.3V, Other inputs pins=0V
Average supply current M5M4V4405C-6,-6S RAS, CAS cycling
from VCC
tRC=tWC=min.
operating (Note 3,4,5) M5M4V4405C-7,-7S output open
Supply current from VcC ,
stand-by
M5M4V4405C
(Note 6) M5M4V4405C(S)
RAS=CAS =VIH, output open
RAS=CASVCC -0.2V
output open
Average supply current
from VCC
refreshing (Note 3,5)
Average supply current
from VCC
Hyper-Page-Mode
(Note 3,4,5)
Average supply current
from VCC, CAS before
RAS refresh mode
(Note 3)
Average supply current
from VCC
Extended-Refresh cycle
Average supply current
from VCC
Self-Refresh cycle (Note 6)
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
(Note 6)
M5M4V4405C(S)
RAS cycling, CAS= VIH
tRC=min.
output open
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
RAS cycling CAS0.2V or CAS
before RAS refresh cycling
RAS0.2V or VCC-0.2V
CAS0.2V or VCC-0.2V
W0.2V (Except for RAS falling
edge) or VCC-0.2V
OE0.2V or VCC-0.2V
A0~A9 0.2V orVCC-0.2V
DQ=open
tRC=125µs, tRAS=tRAS min ~1µs
RAS=CAS0.2V
output open
Limits
Min Typ Max
2.4 Vcc
0 0.4
-5 5
-5 5
80
70
2
0.5
0.05 *
80
70
80
70
70
60
100
100
Note 2: Current flowing into an IC is positive, out is negative.
3: ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.
3 5: Column Addres can be changed once or less while RAS=VIL and CAS=VIH.
Unit
V
V
µA
µA
mA
mA
mA
mA
mA
µA
µA

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MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70˚C, VCC=3.3V±0.3V, Vss=0V, unless otherwise noted)
Symbol
CI (A)
CI (CLK)
CI / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
VI=VSS
f=1MHz
VI=25mVrms
Limits
Min Typ Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Symbol
Parameter
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE low
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
Å@Limits
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
15 20
60 70
30 35
33 38
15 20
55
55
55
15 20
15 20
15 20
15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: An initial pause of 200µs is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh
cycles)ÅDÅ@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@ Å@
Note the RAS may be cycled during the initial pause. And eight initialization cycles are required after prolonged periods (greater than tREF(max)) of
RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 100pF, VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=2mA).
The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that tRCDtRCD(max) and tASCtASC(max) and tCPtCP(max).
9: Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will
increase by amount that tRCD exceeds the value shown.
10: Assumes that tRADtRAD(max) and tASCtASC(max).
11: Assumes that tCPtCP(max) and tASCtASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state(IOUT| ±10µA |) and is
not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
4

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MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70˚C, VCC = 3.3V±0.3V, VSS =0V, unless otherwise noted, see notes 14,15)
Symbol
Parameter
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Refresh cycle time
Refresh cycle time*
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
Delay time, OE high to data
Transition time
(Note 16)
(Note 17)
(Note 18)
(Note 19)
(Note 19)
(Note 20)
(Note 20)
(Note 20)
(Note 21)
Limits
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
16.4
128
40
16.4
128
50
20 45 20 50
55
00
10 13
15 30 15 35
0
0 13
0
0 13
10 10
10 10
00
00
15 20
15 20
15 20
1 50
1 50
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 14: The timing requirements are assumed tT =2ns.
Å@ 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Å@ 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Å@ 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
Å@ 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
Å@ 19: Either tDZC or tDZO must be satisfied.
Å@ 20: Either tRDD or tCDD or tODD must be satisfied.
Å@ 21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH
Read hold time after CAS high
tRRH
Read hold time after RAS high
tRAL Column address to RAS hold time
tCAL Column address to CAS hold time
tORH
RAS hold time after OE low
tOCH
CAS hold time after OE low
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22)
(Note 22)
Limits
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
110 130
60 10000 70 10000
10 10000 13 10000
48 55
15 20
00
00
00
30 35
18 23
15 20
15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5