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(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
The M5M467405/465405BJ,BTP is organized 16777216-word by 4-bit, M5M467805/465805BJ,BTP is organized 8388608-word by
8-bit, and M5M465165BJ,BTP is organized 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS
process, and are suitable for large-capacity memory systems with high speed and low power dissipation.
The use of double-layer aluminum process combined with CMOS technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density. Multiplexed address inputs permit both a reduction in pins and an increase in system
densities.
FEATURES
Type name
RAS
CAS Address OE Cycle
access access access access
time
time time
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M467405BXX-5,5S
M5M467805BXX-5,5S
50
13
25
13
84 300
M5M467405BXX-6,6S
M5M467805BXX-6,6S
60
15
30
15 104 250
M5M465405BXX-5,5S
M5M465805BXX-5,5S
50
13
25
13
84 390
M5M465405BXX-6,6S
M5M465805BXX-6,6S
60
15
30
15 104 325
XX=J,TP
Type name
M5M465165BXX-5,5S
M5M465165BXX-6,6S
RAS
CAS Address OE
access access access access
time
time time
time
Cycle
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
50 13 25 13 84 420
60 15 30 15 104 390
Standard 32 pin SOJ, 32 pin TSOP (M5M467405Bxx/M5M465405Bxx/M5M467805Bxx/M5M465805Bxx)
Standard 50 pin SOJ, 50 pin TSOP (M5M465165Bxx)
Single 3.3 ± 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467405Bxx-5,5S / M5M467805Bxx-5,5S
360.0mW (Max)
M5M467405Bxx-6,6S / M5M467805Bxx-6,6S
324.0mW (Max)
M5M465405Bxx-5,5S / M5M465805Bxx-5,5S
468.0mW (Max)
M5M465405Bxx-6,6S / M5M465805Bxx-6,6S
432.0mW (Max)
M5M465165Bxx-5,5S
504.0mW (Max)
M5M465165Bxx-6,6S
468.0mW (Max)
Self refresh capability*
Self refresh current
400µA (Max)
EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode , OE and W to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
* :Applicable to self refresh version(M5M467405/465405/467805/465805/465165BJ,BTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add Col Add
Refresh
Refresh Cycle
Normal S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467405Bxx A0-A12 A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465405Bxx A0-A11
A0-A11
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467805Bxx A0-A12 A0-A9
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
M5M465805Bxx A0-A11
A0-A10
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
M5M465165Bxx A0-A11 A0-A9
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/64ms
4096/128ms
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1
MITSUBISHI
Jun. 1999
ELECTRIC

No Preview Available !

(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PIN DESCRIPTION
M5M467405Bxx / M5M465405Bxx
Pin Name Function
A0-A12
Address Inputs
DQ1-DQ4 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
M5M467805Bxx / M5M465805Bxx
Pin Name Function
A0-A12
Address Inputs
DQ1-DQ8 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
M5M465165Bxx
Pin Name Function
A0-A11
Address Inputs
DQ1-DQ16 Data Inputs / Outputs
RAS
UCAS
LCAS
Row Address Strobe Input
Upper byte control
Column Address Strobe Input
Lower byte control
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+3.3V)
Vss Ground (0V)
NC No Connection
XX=BJ,BTP
M5M467400/465400BJ,BTP PIN CONFIGURATION (TOP VIEW)
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P0N (400mil SOJ)
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ4
30 DQ3
29 NC
28 NC
27 NC
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467405Bxx, NC...M5M465405Bxx
NC : NO CONNECTION
2
MITSUBISHI
Jun. 1999
ELECTRIC

No Preview Available !

(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467805/465805BJ,BTP PIN CONFIGURATION (TOP VIEW)
Vcc 1
DQ1 2
DQ2 3
DQ3
DQ4
NC
Vcc
4
5
6
7
W8
RAS
A0
A1
A2
9
10
11
12
A3 13
A4 14
A5 15
Vcc 16
32 Vss
31 DQ8
30 DQ7
29 DQ6
28 DQ5
27 Vss
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Vcc
DQ1
DQ2
DQ3
DQ4
NC
Vcc
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ8
30 DQ7
29 DQ6
28 DQ5
27 Vss
26 CAS
25 OE
24 A12/NC(Note)
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
Outline 32P0N (400mil SOJ)
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467800Bxx, NC...M5M465800Bxx
NC : NO CONNECTION
M5M465165BJ,BTP
PIN CONFIGURATION (TOP VIEW)
Vcc 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
Vcc 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
Vcc 12 12
W 13
RAS 14
NC 15
NC 16
NC 17
NC 18
A0 19
A1 20
A2 21
A3 22
A4 23
A5 24
Vcc 25
50 Vss
49 DQ16
48 DQ15
47 DQ14
46 DQ13
45 Vss
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
39 Vss
38 LCAS
37 UCAS
36 OE
35 NC
34 NC
33 NC
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 Vss
Vcc 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
Vcc 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
Vcc 12 12
W 13
RAS 14
NC 15
NC 16
NC 17
NC 18
A0 19
A1 20
A2 21
A3 22
A4 23
A5 24
Vcc 25
50 Vss
49 DQ16
48 DQ15
47 DQ14
46 DQ13
45 Vss
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
39 Vss
38 LCAS
37 UCAS
36 OE
35 NC
34 NC
33 NC
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 Vss
Outline 50P0G (400mil SOJ)
Outline 50P3G (400mil TSOP Normal Bend)
NC : NO CONNECTION
3
MITSUBISHI
Jun. 1999
ELECTRIC

No Preview Available !

(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
The M5M467405(805)/465405(805,165)BJ, BTP provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., EDO mode, CAS before RAS refresh, and delayed-write.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
M5M467405Bxx / M5M465405Bxx / M5M467805Bxx / M5M465805Bxx
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
Inputs
W
NAC
ACT
ACT
ACT
DNC
DNC
NAC
DNC
OE
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
Input
OPN
VLD
VLD
VLD
OPN
OPN
DNC
DNC
Output
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
Refresh Remark
NO
NO
NO
NO
YES
YES
YES
NO
EDO mode
identical
M5M465165Bxx
Operation
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Stand-by
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
LCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
ACT
ACT
DNC
Inputs
UCAS
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
Column
address
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input/Output
DQ1~DQ8 DQ9~DQ16
VLD
OPN
OPN
VLD
VLD
VLD
DIN DNC
DNC
DIN
DIN
OPN
DIN
OPN
VLD
VLD
OPN
OPN
OPN
OPN
Refresh Remark
NO
NO
NO
NO
NO
NO
YES
YES
YES
NO
EDO mode
identical
4
MITSUBISHI
Jun. 1999
ELECTRIC

No Preview Available !

(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467405Bxx / M5M465405Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A11
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
M5M467805Bxx / M5M465805Bxx
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
CAS
RAS
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
(Note)
CLOCK GENERATOR
CIRCUIT
A0~A10
(Note)
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
A0~
A12
(Note)
MEMORY CELL
(67108864 BITS)
Note : Refer to Page 1 (ADDRESS)
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
Vcc (3.3V)
Vss (0V)
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA
INPUTS / OUTPUTS
OE OUTPUT ENABLE
INPUT
5
MITSUBISHI
Jun. 1999
ELECTRIC