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MITMSIUTSBUISBHISI LHSI ILsSIs
M5M44405CJM,T5MP4-4540,-56C,J-,T7P,--55,-S6,,-7-,6-5SS,,--67SS,-7S
EDOED(OHY( PHEYRPEPRAGPAEGMEOMDOED) E41)9441390443-0B4IT-B(IT10(4180547865-7W6O-WRODRBDYB4Y-B4IT-B)ITDY) NDAYNMAICMRICARMAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated
with the high performance CMOS process,and is ideal for large-
capacity memory systems where high speed, low power dissipation,
and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery back-up
application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
FEATURES
Type name
RAS
access
time
(max.ns)
CAS
access
time
(max.ns)
Address
access
time
(max.ns)
OE
access
time
(max.ns)
Cycle
time
(min.ns)
Power
dissipa-
tion
(typ.mW)
M5M44405CXX-5,-5S 50 13 25 13
90 500
M5M44405CXX-6,-6S 60 15 30 15 110 400
M5M44405CXX-7,-7S 70 20 35 20 130 350
XX=J,TP
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 5V±10%supply
Low stand-by power dissipation
CMOS lnput level
5.5mW (Max) *
CMOS lnput level
550µW (Max)
Low operating power dissipation
M5M44405Cxx-5,-5S
687.5mW (Max)
M5M44405Cxx-6,-6S
550.0mW (Max)
M5M44405Cxx-7,-7S
467.5mW (Max)
Self refresh capabiility *
Self refresh current
120µA(max)
Extended refresh capability *
Extended refresh current
120µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-5S,-6S,-7S) capabilities
Early-write mode and OE and W to control output buffer impedance
All inputs, output TTL compatible and low capacitance
1024 refresh cycles every 16.4ms (A0~A9)
1024refresh cycle every 128ms (A0~A9) *
4-bit parallel test mode capability
* : Applicable to self refresh version (M5M44405CJ,TP-5S,-6S,-7S
: option) only
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh
memory for CRT, Frame Buffer memory for CRT
PIN DESCRIPTION
Pin name
Function
A0~A9
Address Inputs
DQ1~DQ4 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+5V)
1 Vss
Ground (0V)
M5M44405CJ,TP-5,-5S:Under development
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P0J (300mil SOJ)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P3Z-E (300mil TSOP)

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MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
FUNCTION
The M5M44405CJ, TP provide, in addition to normal read, write,
and read-modify-write operations,a number of other functions, e.g.,
hyper page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Read
Operation
RAS
ACT
CAS
ACT
Inputs
W
NAC
OE
ACT
Row
address
APD
Column
address
APD
Write (Early write)
ACT ACT ACT DNC APD APD
Write (Delayed write)
ACT ACT ACT NAC APD APD
Read-modify-write
ACT ACT ACT ACT APD APD
RAS-only refresh
ACT NAC DNC DNC APD DNC
Hidden refresh
ACT ACT DNC ACT DNC DNC
CAS before RAS refresh
ACT ACT NAC DNC DNC DNC
Self refresh *
ACT ACT NAC DNC DNC DNC
Stand-by
NAC DNC DNC DNC DNC DNC
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
Input/Output
Input Output
OPN VLD
APD OPN
APD IVD
APD VLD
DNC OPN
OPN VLD
DNC OPN
DNC
DNC
OPN
OPN
Refresh Remark
YES
YES
YES
YES
YES
YES
YES
YES
NO
Hyper-
Page
mode
identical
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT CAS
ROW ADDRESS RAS
STROBE INPUT
WRITE CONTROL W
INPUT
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CLOCK GENERATOR
CIRCUIT
A0~A9
COLUMN DECODER
ROW &
COLUMN
ADDRESS
BUFFER
A0~ ROW
A9 DECODER
SENSE REFRESH
AMPLIFER & I /O CONTROL
MEMORY CELL
(4,194,304 BITS)
(4)
DATA IN
BUFFERS
(4)
DATA OUT
BUFFERS
VCC (5V)
VSS (0V)
DQ1
DQ2 DATA
DQ3 INPUTS / OUTPUTS
DQ4
OE
OUTPUT
INPUT
ENABLE
M5M44405CJ,TP-5,-5S:Under development

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MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
VO
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ta=25˚C
Ratings
-1~7
-1~7
-1~7
50
1000
0~70
-65~150
Unit
V
V
V
mA
mW
˚C
˚C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)
Symbol
Parameter
VCC Supply voltage
VSS Supply voltage
VIH High-level input voltage, all inputs
VIL
Low-level input voltage
DQ1~4
others
Note 1 : All voltage values are with respect to Vss.
Limits
Min Nom Max
4.5 5
5.5
00
2.4
0
6.0
-1.0 0.8
-2.0 0.8
Unit
V
V
V
V
V
ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC= 5V±10%, VSS=0V, unless otherwise noted) (Note 2)
Symbol
VOH
VOL
IOZ
II
ICC1 (AV)
ICC2 (AV)
ICC3 (AV)
Parameter
Test conditions
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current M5M44405C-5,-5S
from Vcc, operating
M5M44405C-6,-6S
(Note 3,4,5) M5M44405C-7,-7S
Supply current from Vcc ,
stand-by
(Note 6)
M5M44405C
M5M44405C(S)
Average supply current M5M44405C-5,-5S
from Vcc, refreshing
M5M44405C-6,-6S
(Note 3,5) M5M44405C-7,-7S
IOH =–5mA
IOL = 4.2mA
Q floating 0V VOUT 5.5V
0V VIN +6.5V, Other inputs pins=0V
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
RAS= CAS VCC–0.5V
output open
RAS cycling, CAS= VIH
tRC=min.
output open
Limits
Min Typ
2.4
0
-10
-10
ICC4(AV)
ICC6(AV)
ICC8(AV)
ICC9(AV)
Average supply current M5M44405C-5,-5S
from Vcc, Hyper-Page- M5M44405C-6,-6S
Mode
(Note 3,4,5) M5M44405C-7,-7S
Average supply current
M5M44405C-5,-5S
from Vcc, CAS before
M5M44405C-6,-6S
RAS refresh mode (Mote 3) M5M44405C-7,-7S
Average supply current
from Vcc,
Extended-Refresh cycle
(Note 6)
Average supply current
from Vcc, Self-Refresh M5M44405C(S)
cycle
(Note 6)
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
RAS cycling CAS 0.2V or CAS
before RAS refresh cycling
RAS 0.2V or VCC-0.2V
CAS 0.2V or VCC-0.2V
W 0.2V(Except for RAS falling edge)
or VCC-0.2V
OE 0.2V or VCC-0.2V
A0~A9 0.2V or VCC-0.2V,
DQ=open
tRC=125µs, tRAS=tRAS min~1µs
RAS=CAS 0.2V
output open
Note 2 : Current flowing into an IC is positive, out is negative.
Note 3 : ICC1(AV), ICC3 (AV), ICC4(AV) and ICC6(AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
Note 4 : ICC1(AV) and ICC4(AV) are dependent on output loading. Specified values are obtained with the output open.
Note 5 : Column Address can be changed once or less while RAS=VIL and CAS=VIH.
3 M5M44405CJ,TP-5,-5S:Under development
Max
Vcc
0.4
10
10
125
100
85
2
1
0.1
125
100
85
125
100
85
105
85
75
120
120
Unit
V
V
µA
µA
mA
mA
mA
mA
mA
µA
µA

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MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
CAPACITANCE (Ta=0~70˚C, VCC= 5V±10%, VSS=0V, unless otherwise noted)
Symbol
CI (A)
CI (CLK)
CI / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
VI=VSS
f=1MHz
VI=25mVrms
Limits
Min Typ Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC= 5V±10%, VSS=0V, unless otherwise noted, see notes 6,14,15)
Symbol
Parameter
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
Limits
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Min Max Min Max Min Max
(Note 7,8)
13
15
20
(Note 7,9)
50
60
70
(Note 7,10)
25
30
35
(Note 7,11)
28
33
38
(Note 7)
13
15
20
555
(Note 13) 5 5 5
(Note 7) 5 5 5
(Note 12)
13
15
20
(Note 12)
13
15
20
(Note 12,13)
13
15
20
(Note 12,13)
13
15
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6 : An initial pause of 200µs is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause . And eight initialization cycles are required after prolonged periods (greater than tREF(max)) of RAS
inactivity before proper device operation is achieved.
Note 7 : Measured with a load circuit equivalent to 2TTL and 100pF.
The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL).
Note 8 : Assumes that tRCD tRCD(max) and tASC tASC(max) and tCP tCP(max).
Note 9 : Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will
increase by amount that tRCD exceeds the value shown.
Not 10 : Assumes that tRAD tRAD(max) and tASC tASC(max).
No t11 : Assumes that tCP tCP(max) and tASC tASC(max).
No t12 : tOEZ(max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ±10µA ) and is not
reference to VOH(min) or VOL(max).
Not 13 : Output is disabled after both RAS and CAS go to high.
4 M5M44405CJ,TP-5,-5S:Under development

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MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70˚C, VCC= 5V±10%, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
Parameter
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S Unit
Min Max Min Max Min Max
tREF Refresh cycle time
16.4 16.4 16.4 ms
tREF Refresh cycle time *
128 128 128 ms
tRP RAS high pulse width
tRCD Delay time, RAS low to CAS low
30 40 50
ns
(Note 16) 18
37 20
45 20
50
ns
tCRP Delay time, CAS high to RAS low
tRPC Delay time, RAS high to CAS low
tCPN CAS high pulse width
5 55
0 00
8 10 13
ns
ns
ns
tRAD Column address delay time from RAS low
(Note 17) 13
25 15
30 15
35
ns
tASR Row address setup time before RAS low
0 00
ns
tASC Column address setup time before CAS low (Note 18) 0 10 0 13 0 13 ns
tRAH Row address hold time after RAS low
tCAH Column address hold time after CAS low
8 10 10
8 10 10
ns
ns
tDZC Delay time, data to CAS low
tDZO Delay time, data to OE low
tRDD Delay time, RAS high to data
(Note 19) 0 0 0
(Note 19) 0 0 0
(Note 20) 13 15 20
ns
ns
ns
tCDD Delay time, CAS high to data
(Note 20) 13 15 20
ns
tODD
Delay time, OE high to data
(Note 20) 13 15 20
ns
tT Transition time
(Note 21) 1 50 1 50 1 50 ns
Note 14 : The timing requirements are assumed tT=2ns.
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Note 17 : tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
Note 18 : tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
Note 19 : Either tDZC or tDZO must be satisfied.
Note 20 : Either tRDD or tCDD or tODD must be satisfied.
Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Parameter
tRC Read cycle time
tRAS RAS low pulse width
tCAS CAS low pulse width
tCSH CAS hold time after RAS low
tRSH RAS hold time after CAS low
tRCS Read Setup time before CAS low
tRCH Read hold time after CAS high
tRRH Read hold time after RAS high
tRAL Column address to RAS hold time
tCAL Column address to CAS hold time
tORH
RAS hold time after OE low
tOCH
CAS hold time after OE low
Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
Limits
M5M44405C-5,-5S M5M44405C-6,-6S M5M44405C-7,-7S
Min Max Min Max Min Max
90 110 130
50 10000 60 10000 70 10000
8 10000 10 10000 13 10000
40 48 55
13 15 20
0 00
(Note 22) 0
00
(Note 22) 0
00
25 30 35
13 18 23
13 15 20
13 15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
M5M44405CJ,TP-5,-5S:Under development