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Intel® 80303 I/O Processor
Design Guide
April 2002
Order Number: 273308-006

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Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked reservedor undefined.Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 80303 I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
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Copyright© Intel Corporation, 2002
*Other brands and names are the property of their respective owners.
2 Intel® 80303 I/O Processor Design Guide

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Contents
1.0 Introduction......................................................................................................................... 7
2.0 Intel® 80303 I/O Processor Ball Map ................................................................................. 8
2.1 Intel® 80303 I/O Processor H-PBGA Signal Ball Map........................................... 8
3.0 Routing Guidelines ............................................................................................................. 9
3.1 Trace Length Limits............................................................................................... 9
4.0 Intel® 80303 I/O Processor Memory Subsystem..............................................................10
4.1 ROM, SRAM, or Flash Guidelines.......................................................................10
4.1.1 Layout Guidelines...............................................................................11
4.1.2 Wait State Profiles ..............................................................................11
4.2 SDRAM Guidelines .............................................................................................12
4.2.1 Layout Guidelines...............................................................................13
4.2.2 SDRAM Clocking................................................................................20
4.2.3 SDRAM Power Failure Guidelines .....................................................21
4.2.4 System Assumptions ..........................................................................21
4.2.5 External Logic Required for Power Failure.........................................22
5.0 Interrupt Routing...............................................................................................................24
5.1 Intel® 80303 I/O Processor Implementation on a MotherBoard ..........................24
5.2 Intel® 80303 I/O Processor Implementation on an Add-in Card..........................25
6.0 Clocking Guidelines..........................................................................................................26
6.1 Layout Guidelines for Add-in Cards ....................................................................26
6.2 Layout Guidelines for Motherboards ...................................................................27
7.0 Intel® 80303 I/O Processor Signals Requiring Pull-Up/Down Resistors ..........................29
8.0 Intel® 80303 I/O Processor 5 V and 3.3 V Design Considerations ..................................31
8.1 VCC5REF Pin Requirement (VDIFF) ......................................................................31
8.2 VCCPLL Pins Requirement ...................................................................................32
8.3 Pull-ups and Pull-down Resistors........................................................................32
8.4 FAIL# Pin Implementation ...................................................................................32
9.0 Processor Power Supply Decoupling ...............................................................................33
9.1 High Frequency Decoupling ................................................................................33
10.0 Intel® 80303 I/O Processor Based Reference Design .....................................................35
11.0 Debug Connector Recommendations ..............................................................................36
11.1 PBGA Sockets and Headers ...............................................................................36
11.2 Logic Analyzer Connectivity ................................................................................38
11.3 JTAG Connector and Test Interface....................................................................39
11.3.1 Intel® 80303 I/O Processor JTAG Emulator .......................................39
11.3.2 Intel® 80303 I/O Processor Target Debug Interface Connector .........39
11.3.3 Connecting The Emulator To The Target ...........................................41
11.3.4 Other Tools.........................................................................................42
Intel® 80303 I/O Processor Design Guide
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12.0 Design for Manufacturability............................................................................................. 43
13.0 Thermal Solutions ............................................................................................................ 44
13.1 Thermal Recommendations ................................................................................ 44
13.2 3-Dimensional View: Processor With Heat Sink Attached .................................. 45
13.3 PCB Heatsink Hole Dimensions.......................................................................... 46
13.4 Clearances of PCI Board and Components ........................................................ 48
13.5 Heat Sink Information.......................................................................................... 49
13.5.1 Socket Information ............................................................................. 49
13.5.2 Socket-Header Vendor....................................................................... 49
13.5.3 Burn-in Socket Vendor ....................................................................... 49
13.5.4 Shipping Tray Vendor......................................................................... 50
13.5.5 JTAG Emulator Vendor ...................................................................... 50
14.0
References....................................................................................................................... 51
14.1 Related Documents............................................................................................. 51
14.2 Electronic Information ......................................................................................... 51
Figures
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540L H-PBGA Diagram (Bottom View) ................................................................. 8
Examples of Stubless and Short Stub Traces....................................................... 9
4 Mbyte Flash Memory System........................................................................... 11
Dual-Bank SDRAM Memory Subsystem............................................................. 13
Single DIMM Address, Data and Control Signals ............................................... 15
Dual DIMM Address, Data and Control Signals .................................................. 15
Single DIMM SCE[1:0] Signals ........................................................................... 16
Dual DIMM SCE[1:0] Signals .............................................................................. 16
Single DIMM SCKE[1:0] Signals ......................................................................... 17
Dual DIMM SCKE[1:0] Signals............................................................................ 17
Single DIMM SDQM[7:0] Signals ........................................................................ 17
Dual DIMM SDQM[7:0] Signals........................................................................... 18
Discrete SDRAM Address and Control Signals .................................................. 18
Discrete SDRAMs Data Signals.......................................................................... 19
Discrete SDRAMs DQM[7:0] Signals .................................................................. 19
Clocking for a Dual-Bank SDRAM DIMM ............................................................ 20
External Power Failure State Machine................................................................ 22
External Power Failure Logic in the System ....................................................... 22
Logic Generating PWRDELAY and SYSTEM_RST#.......................................... 23
PWRDELAY Timings .......................................................................................... 23
Example Secondary PCI Connector Interrupt Routing........................................ 25
PCI Add-in Card Example Configuration............................................................. 26
Motherboard Example Configuration .................................................................. 28
VCC5REF Current-Limiting Resistor...................................................................... 31
VCCPLL Lowpass Filter ........................................................................................ 32
Recommended FAIL# Circuit .............................................................................. 32
High-Frequency Capacitor Values and Layout ................................................... 34
540L PBGA Header ............................................................................................ 36
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29 540L PBGA Socket .............................................................................................37
30 JTAG Emulator Connector (Top View)................................................................39
31 Conceptual 3-D View of Processor with a Heat Sink ..........................................45
32 Hole Dimensions for Passive Heatsink ...............................................................46
33 Board Level Keep Out Areas...............................................................................47
34 Clearances of PCI Board and Components ........................................................48
35 Decoupling Schematic.........................................................................................53
36 Primary PCI Interfacel Schematic .......................................................................54
37 Memory Controllerl Schematic ............................................................................55
38 Flash ROM and UARTl Schematic......................................................................56
39 LEDs Schematic..................................................................................................57
40 Logic Analyzer I/Fl Schematic .............................................................................58
41 SDRAM 168-Pin DIMMl Schematic.....................................................................59
42 Secondary PCI/80960 Corel Schematic..............................................................60
43 Secondary PCI Bus 1/2l Schematic ....................................................................61
44 SPCI Pull-Upsl Schematic...................................................................................62
45 Barrtery/Monitorl Schematic ................................................................................63
46 SDRAM +3.3 V Referencel Schematic................................................................64
47 SCKE Control Schematic ....................................................................................65
Tables
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Flash Interface Signals........................................................................................10
ROM, SRAM, or Flash Wait State Profile Programming .....................................11
SDRAM Interface Signals....................................................................................12
Drive Strength Programmability Options .............................................................14
Intel® 80303 I/O Processor Interrupt Routing Signals .........................................24
Memory Controller, Core and JTAG Signals .......................................................29
I2C Bus Signals ...................................................................................................29
PCI Signals..........................................................................................................30
VDIFF Specification for Dual-Power Supply Requirements (3.3 V, 5 V)...............31
Logic Analyzer Header Definitions (Mictor) .........................................................38
Intel® 80303 I/O Processor Debug Connector Wiring .........................................40
Intel® 80303 I/O Processor with PC-1149.1/100F (cable P/N AS01090025-Ax) 41
Intel® 80303 I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx).42
H-PBGA Package Characteristics.......................................................................44
Heat Sink Vendors and Contacts ........................................................................49
Socket-Header Vendor........................................................................................49
Burn-in Socket Vendor ........................................................................................49
Shipping Tray Vendor..........................................................................................50
JTAG Emulator Vendor .......................................................................................50
Related Documentation.......................................................................................51
Electronic Information..........................................................................................51
IQ80303 Bill of Materials .....................................................................................66
540 L H-PBGA - Ballpad Order ...........................................................................69
Intel® 80303 I/O Processor Design Guide
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