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Intel® 80303 I/O Processor
Design Guide
April 2002
Order Number: 273308-006

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Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
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Designers must not rely on the absence or characteristics of any features or instructions marked reservedor undefined.Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 80303 I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
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Contents
1.0 Introduction......................................................................................................................... 7
2.0 Intel® 80303 I/O Processor Ball Map ................................................................................. 8
2.1 Intel® 80303 I/O Processor H-PBGA Signal Ball Map........................................... 8
3.0 Routing Guidelines ............................................................................................................. 9
3.1 Trace Length Limits............................................................................................... 9
4.0 Intel® 80303 I/O Processor Memory Subsystem..............................................................10
4.1 ROM, SRAM, or Flash Guidelines.......................................................................10
4.1.1 Layout Guidelines...............................................................................11
4.1.2 Wait State Profiles ..............................................................................11
4.2 SDRAM Guidelines .............................................................................................12
4.2.1 Layout Guidelines...............................................................................13
4.2.2 SDRAM Clocking................................................................................20
4.2.3 SDRAM Power Failure Guidelines .....................................................21
4.2.4 System Assumptions ..........................................................................21
4.2.5 External Logic Required for Power Failure.........................................22
5.0 Interrupt Routing...............................................................................................................24
5.1 Intel® 80303 I/O Processor Implementation on a MotherBoard ..........................24
5.2 Intel® 80303 I/O Processor Implementation on an Add-in Card..........................25
6.0 Clocking Guidelines..........................................................................................................26
6.1 Layout Guidelines for Add-in Cards ....................................................................26
6.2 Layout Guidelines for Motherboards ...................................................................27
7.0 Intel® 80303 I/O Processor Signals Requiring Pull-Up/Down Resistors ..........................29
8.0 Intel® 80303 I/O Processor 5 V and 3.3 V Design Considerations ..................................31
8.1 VCC5REF Pin Requirement (VDIFF) ......................................................................31
8.2 VCCPLL Pins Requirement ...................................................................................32
8.3 Pull-ups and Pull-down Resistors........................................................................32
8.4 FAIL# Pin Implementation ...................................................................................32
9.0 Processor Power Supply Decoupling ...............................................................................33
9.1 High Frequency Decoupling ................................................................................33
10.0 Intel® 80303 I/O Processor Based Reference Design .....................................................35
11.0 Debug Connector Recommendations ..............................................................................36
11.1 PBGA Sockets and Headers ...............................................................................36
11.2 Logic Analyzer Connectivity ................................................................................38
11.3 JTAG Connector and Test Interface....................................................................39
11.3.1 Intel® 80303 I/O Processor JTAG Emulator .......................................39
11.3.2 Intel® 80303 I/O Processor Target Debug Interface Connector .........39
11.3.3 Connecting The Emulator To The Target ...........................................41
11.3.4 Other Tools.........................................................................................42
Intel® 80303 I/O Processor Design Guide
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