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M02050-15
3.3/5V Limiting Amplifier for Applications to 2.5 Gbps
The M02050-15 is an integrated high-gain limiting amplifier. The M02050-15 features PECL outputs and is intended
for use in applications to 2.5 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02050-15
can operate with a 3.3V or 5V supply.
Rate select is supported for SFP applications and/or to achieve optimum sensitivity at data rates 1.25 Gbps.
When rate select is high, optimum sensitivity is achieved at 2.5 Gbps.
The M02050-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input sig-
nal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
Other available solutions: M02049-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
M02040-15 3.3/5V Limiting Amplifier for Applications to 2.125 Gbps (PECL outputs)
M02043-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
1.25 Gbps and 4.25 Gbps SFP reference designs available on Mindspeed.com
Applications
• 2.5 Gbps STM-16/OC-48 SDH/SONET
• 1.06, 2.12 and 4.24 Gbps Fibre Channel
• 1.25 Gbps Ethernet
• 1.25 Gbps SDH/SONET
• 2.67 Gbps SDH/SONET with FEC
Features
• Operates with a 3.3V or 5V supply
• 3.5 mV typical input sensitivity at 2.5 Gbps
• PECL outputs
• Rate Selection for 1.25 Gbps operation
• Average Receive power monitor output (RSSIAVG)
• Peak-to-peak Receive power monitor output (RSSIPP)
• On-chip DC offset cancellation circuit
• Low power (< 180 mW at 3.3V)
• Output Jam Function
• 16 pin 3x3 QFN package
Typical Applications Diagram
+3.3 V
Photodiode
RATESELControl RATE SEL
IREF
12.1 kΩ
AC-Coupled
to TIA
DINP
MT02I0A13
VTT
Biasing
Limiting
Amplifier
MON
DINN
Jam
Output
Buffer
RxAVGIN
RSSIAVG
REXT
Level
Shift
Offset cancel
Level
Detect
Comparator
Threshold
Setting
Circuit
Regulator
STSET
RST
VCC3 VCC
optional
PECLP
PECLN
Clock Data
Recovery
Unit
RSSIPP
AC or DC Coupled
(as described in
Applications Information)
LOS
02050-DSH-002-F
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
August 2005

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Ordering Information
Part Number
Package
Operating Temperature
M02050-15 *
M02050-15 in QFN16 package
–40 °C to 85 °C
M02050-15EVM
Evaluation board with M02050-15
–40 °C to 85 °C
* The letter “G” designator after the part number indicates that the device is RoHS-compliant. Refer to www.mindspeed.com for additional
information.
Revision History
Revision
F
Level
Final
E Final
D Preliminary
Date
August 2005
July 2005
April 2005
ASIC
Revision
Description
-15 Correct Jam connection in block diagram and typical applications figures.
Correct IREF figure (reference current generation).
-15 In the DC specifications, update ICC, RINDIFF and RSSIavg; added note 2;
moved RSSIavg from ac specifications. In the ac specifications update
VIN(MIN), VLOS, DJ, RJ and tr/tf; add specifications for LOS assert and
deassert. Updated RST values and the typical LOS curve (Figure 4-3 - Figure 4-
5). Added typical hysteresis curve (Figure 4-6).
-15 Separated the M02049 and M02050 data sheets. New document number for
the M02049 is 02049-15-DSH-002-D.
Update the following DC specifications: ICC, RINDIFF and VOH. Update the
following ac specifications: VIN(MIN), vn, VLOS, HYS, DJ, RJ, tr/tf, TLOS_ON, and
TLOS_OFF. Update RST and RSSI values for this revision of the part.
M02050 Typical Eye Diagram
M02050-15 Pin Configuration
10 mVPP2.d5iffGebrepnstial input
160 mV/div
80 ps/div
GND
VCC
PECLN
PECLP
1
4
16 13
Center Pad
Connect to GND
58
12 RxAvgIN
GND
DINN
9 DINP
02050-DSH-002-F
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1.0 Product Specification
1.1 Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reli-
able operation at these extremes for any length of time is not implied.
NOTE:
The package bottom should be adequately grounded to ensure correct thermal performance,
and it is recommended that vias are inserted through to a lower ground plane.
Table 1-1. Absolute Maximum Ratings
Symbol
Parameter
VCC
TSTG
PECLP, PECLN
Power supply voltage (VCC-GND)
Storage temperature
PECL Output pins voltage
I(PECLP), I(PECLN)
|DINP - DINN|
DINP, DINN
PECL Output pins maximum continuous current (delivered to load)
Data input pins differential voltage
Data input pins voltage meeting |DINP - DINN| requirement
STSET
JAM
Signal detect threshold setting pin voltage
Output enable pin voltage
LOS Status Output pins voltage
Rate_Sel
Rate Select input pin voltage
IREF
I(RSSIAVG)
RSSIPP
I(LOS)
Current into Reference input
Current into RSSIavg input
RSSIPP pin voltage
Current into Loss of Signal pin
Rating
-0.5 to +5.75
-65 to +150
VCC - 2 to VCC + 0.4
30
0.80
GND to VCC3 + 0.4
GND to VCC3 + 0.4
GND to VCC + 0.4
GND to VCC + 0.4
GND to VCC + 0.4
+0 to -120
+0 to -3
GND to VCC3 + 0.4
+3000 to -100
Units
V
°C
V
mA
V
V
V
V
V
V
µA
mA
V
µA
02050-DSH-002-F
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Product Specification
1.2 Recommended Operating Conditions
Table 1-2. Recommended Operating Conditions
Parameter
Power supply: (VCC-GND) (apply no potential to VCC3) or
(VCC3-GND) (connect VCC to same potential as VCC3)
Junction temperature
Operating ambient
Rating
+5V ± 7.5% or
+3.3V ± 7.5%
-40 to +110
-40 to +85
Units
V
°C
°C
1.3 DC Characteristics
VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-3. DC Characteristics
Symbol
Parameter
Conditions
Min
ICC
VOUTLpecl
VOUTHpecl
Supply Current
PECL Output Low Voltage (2)
(PECLP, PECLN)
PECL Output High Voltage (2)
(PECLP, PECLN)
Includes PECL load
Single ended; 50 load to VCC-2V
Single ended; 50load to VCC-2V
VCC-1.81
VCC-1.025
RINDIFF Differential Input Resistance Measured between DINP and DINN
90
VOH LOS Output High Voltage
External 4.7-10 kpull up to VCC
2.75
VOL LOS Output Low Voltage
External 4.7-10 kpull up to VCC
0
VIH
VIL
RSSIavg
Logic Input High Voltage
JAM, RATESEL
Logic Input Low Voltage
JAM, RATESEL
Average received signal
strength indicator range
± 15% accuracy
2.7
5
Notes:
1. RATESEL high (high bandwidth operation). Typical supply current decreases by 1.5 mA in low rate mode.
2. Limits apply between 0°C to +85°C. Below 0 °C the minimum decreases by up to 40 mV.
Typ
54 (1)
VCC-1.71
VCC-0.952
110
VCC
Max
65
VCC-1.62
VCC-0.88
130
0.4
VCC
0.8
2000
Units
mA
V
V
V
V
V
V
µA
02050-DSH-002-F
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Product Specification
1.4 AC Characteristics
VCC = +3.3V ± 7.5% or +5V ± 7.5%, TA = -40°C to +85°C, input bit rate = 2.5 Gbps 223-1 PRBS, high rate
mode (RATESEL = High) unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-4. AC Characteristics
Symbol
Parameter
Conditions
Min Typ Max Units
VIN(MIN)) Differential Input Sensitivity
VI(MAX)
Input Overload
1.25 Gbps, BER < 10-12, low rate mode
(RATESEL = low)
2.125 Gbps, BER < 10-12, low rate mode
(RATESEL = low)
2.5 Gbps, BER < 10-12
BER < 10-12, differential input 2.5 Gbps
BER < 10-12, single-ended input, 2.5 Gbps
– 2 2.75 mV
– 3 4.75 mV
– 3.5 5 mV
1200
– mV
600 –
– mV
vn
RSSIpp
RMS Input Referred Noise
Peak-to-peak received signal
strength indicator range
RATESEL = high
Differential input signal range
– 280 – µVRMS
4 – 100 mV
BWLF
Small-Signal –3dB Low Frequency Excluding AC coupling capacitors
Cutoff
– 25 – kHz
DJ
RJ
tr / tf
TRATESEL
Deterministic Jitter (includes DCD) K28.5 pattern at 2.5 Gbps, 10 mVPP input
Random Jitter
10 mVPP input
Data Output Rise and Fall Times
Rate select assert / deassert time
20% to 80%; outputs terminated into 50 Ω;
10 mVPP input
RATESEL = High
RATESEL = Low
Time from when rate select is asserted high or low
until amplifier is performing at selected bandwidth
18 25 ps
3.9 – psRMS
ps
110 125
145 180
– 10
µs
VLOS
LOS Programmable Range
HYS Signal Detect Hysteresis
Differential inputs
electrical; across LOS programmable range
5 – 55 mV
2 3.5 5.5 dB
ASSERTLOW Low Input LOS Assert threshold RST = 7.50 k, differential input
DEASSERTLOW Low Input LOS De-Assert threshold RST = 7.50 k, differential input
ASSERTMED Medium Input LOS Assert threshold RST = 6.81 k, differential input
DEASSERTMED Medium Input LOS De-Assert
threshold
RST = 6.81 k, differential input
3.5 4.9
– mVPP
– 7.8 11.3 mVPP
8.4 11.7
– mVPP
– 17.0 24.6 mVPP
ASSERTHI
DEASSERTHI
TLOS_ON
High Input LOS Assert threshold RST = 6.19 k, differential input
High Input LOS De-Assert threshold RST = 6.19 k, differential input
Time from LOS state until LOS
output is asserted (1)
LOS assert time after 1 VPP input signal is turned
off; signal detect level set to 10 mV
16.6 23.2
– mVPP
– 33.4 48.4 mVPP
2.3 – 80 µs
02050-DSH-002-F
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