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MN103SFJ7/N0/N4 Series, MN103SFN1/N5 Series, MN103SFN2/N6 Series
32-bit Single-chip Microcontroller
PubNo. 232N6-014E
1.1 Overview
1.1.1 Overview
The MN103S is a 32-bit microcontroller combining ease of use intended for programs development in the C lan-
guage with a simple, high-performance architecture made possible through pursuit of cost performance.
Built around a compact 32-bit CPU with a basic instruction word length of 1 byte, this LSI includes internal mem-
ory for instructions and data, DMA controller, a clock generator, bus controller, interrupt controller, watchdog
timer, standard peripheral circuitry such as timers and serial interfaces, PWM circuit best suited to controlling 3-
phase motors and A/D converters for motor position control. The MN103S Series’ high-speed CPU coupled with
abundance of peripheral features provides an easy means of developing low-cost, high-performance and multi-
functional system on LSI for motor and power control applications requiring fast response - a feature previously
unavailable with conventional microcontrollers.
1.1.2 Product Summary
This manual describes the following models.
Table:1.1.1 Product Summary
Model
MN103SFJ7A
MN103SFN0D
MN103SFN0X
MN103SFN0G
MN103SFN0Y
MN103SFN1D
MN103SFN1X
MN103SFN1G
MN103SFN1Y
MN103SFN2D
MN103SFN2X
MN103SFN2G
MN103SFN2Y
MN103SFN4D
MN103SFN4X
MN103SFN4G
MN103SFN4Y
MN103SFN5D
MN103SFN5X
MN103SFN5G
MN103SFN5Y
MN103SFN6D
MN103SFN6X
MN103SFN6G
MN103SFN6Y
ROM
Size
32KB
64KB
128KB
64KB
128KB
64KB
128KB
64KB
128KB
64KB
128KB
64KB
128KB
RAM
Size
2KB
4KB
8KB
6KB
8KB
4KB
8KB
6KB
8KB
4KB
8KB
6KB
8KB
4KB
8KB
6KB
8KB
4KB
8KB
6KB
8KB
4KB
8KB
6KB
8KB
Pins
TQFP 48 pin
Timer
(8bit/16bit)
8/1
QFP 44 pin
TQFP 48 pin
8/2
TQFP 64 pin
LQFP 64 pin
12/3
TQFP 80 pin
12/5
QFP 44 pin
TQFP 48 pin
8/2
TQFP 64 pin
LQFP 64 pin
12/3
TQFP 80 pin
12/5
PWM
1
1
2
2
1
2
2
Serial I/F
2
2
3
3
2
3
3
A/D
2
2
2
2
2
2
2
VGA
-
-
-
-
1
2
2
Publication date: March 2017

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MN103SFJ7/N0/N4 Series, MN103SFN1/N5 Series, MN103SFN2/N6 Series
32-bit Single-chip Microcontroller
PubNo. 232N6-014E
1.2 Hardware Functions
CPU Core
MN103S core
4 GB of address space (for instructions / data)
LOAD/STORE architecture with 5-stage pipeline
46 basic instructions + 8 extension instructions
6 addressing modes
Instruction set of 1 byte in word length
Extension arithmetic unit incorporated
(high-speed multiply instruction, high-speed division instruction etc.)
Machine cycle: 16.7 ns (oscillation frequency: 10 MHz, 6 multiplying)
Operation mode: NORMAL mode, SELLP mode, HALT mode, STOP mode
Oscillation Circuit External oscillation (crystal/ ceramic)
Clock multiply circuit Oscillation clock can be multiplied by from 3 to 12
Internal Memory
ROM 32 K/64 K/128 Kbytes RAM 2 K/4 K/6 K/8 Kbytes
The ROM/RAM size is different in each product.
Please refer to [2.6.2 Memory Map] for details.
DMA Controller*
Numbr of channels : 1 channel
Startup sources : 15 sources (MN103SFN0/N4 series)
20 sources (MN103SFN1/N5 series)
22 sources (MN103SFN2/N6 series)
(External interrupts : Max 12 sources,
Serial Interface : Max 9 sources,
Software start :
1 sources)
Transfer modes : 3 modes (One word transfer, Burst transfer, Intermittent transfer)
* There is not the function in the MN103SFJ7A.
Interrupts
Non-maskable interrupts
Watchdog timer overflow interrupts
System error interrupts
Fail safe function interrupts
Internal interrupts (Level interrupt)
MN103SFJ7A
: 23 interrupts
MN103SFN0/N4 series: 29 interrupts
MN103SFN1/N5 series: 42 interrupts
MN103SFN2/N6 series: 48 interrupts
<Timer Interrupts>
Timer 0 underflow interrupt
Timer 1 underflow interrupt
Timer 2 underflow interrupt
Timer 3 underflow interrupt
Timer 4 underflow interrupt
Timer 5 underflow interrupt
Timer 6 underflow interrupt
Timer 7 underflow interrupt
Timer 8 underflow interrupt
Timer 9 underflow interrupt
Timer 10 underflow interrupt
Timer 11 underflow interrupt
Timer 16 overflow/underflow interrupt
Publication date: March 2017

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MN103SFJ7/N0/N4 Series, MN103SFN1/N5 Series, MN103SFN2/N6 Series
32-bit Single-chip Microcontroller
PubNo. 232N6-014E
Timer 16 compare/capture A interrupt
Timer 16 compare/capture B interrupt
Timer 17 overflow/underflow interrupt
Timer 17 compare/capture A interrupt
Timer 17 compare/capture B interrupt
Timer 18 overflow/underflow interrupt
Timer 18 compare/capture A interrupt
Timer 18 compare/capture B interrupt
Timer 19 overflow/underflow interrupt
Timer 19 compare/capture A interrupt
Timer 19 compare/capture B interrupt
Timer 20 overflow/underflow interrupt
Timer 20 compare/capture A interrupt
Timer 20 compare/capture B interrupt
<Serial Interface>
Serial 0 reception end interrupts
Serial 0 communication/transmission end interrupts
Serial 1 reception end interrupts
Serial 1 communication/transmission end interrupts
Serial 2 reception end interrupts
Serial 2 communication/transmission end interrupts
<PWM>
PWM0 overflow interrupts
PWM0 underflow interrupts
PWM0 synchronous A/D start A
PWM0 synchronous A/D start B
PWM1 overflow interrupts
PWM1 underflow interrupts
PWM1 synchronous A/D start A
PWM1 synchronous A/D start B
<A/D>
A /D 0 conversion end interrupt
A /D 0 conversion end B interrupt
A /D 1 conversion end interrupt
A /D 1 conversion end B interrupt
<DMA>
DMA transfer end interrupt
DMA request after DMA transfer end interrupt
DMA transfer request overflow interrupt
External interrupts(Level interrupt)
MN103SFJ7A
: 4 interrupts
MN103SFN0/N4 series : 8 interrupts
MN103SFN1/N5 series : 10 interrupts
MN103SFN2/N6 series : 12 interrupts
External interrupt pins
Interrupt detection condition
: From IRQ00 to IRQ11
: Each edge, both edges, high-level and low-level detection
Each interrupt detection condition is able to filtering with
the noise filter
Publication date: March 2017