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1.1 Overview
MN101EFA8/A7/A3/A2/G0 Series
8-bit Single-chip Microcontroller
PubNo. 216A8-015E
1.1.1 Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series)
incorporate multiple types of peripheral functions. This chip series is well suited for automotive power window,
camera, TV, CD, printer, telephone, home appliance, PPC, fax machine, music instrument and other applications.
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim-
ple efficient instruction set. MN101EFA7G/A8G/A2G/A3G/G0G have an internal 128 KB of ROM and 6 KB of
RAM. MN101EFA7D/A8D/A2D/A3D/G0D have an internal 64 KB of ROM and 4 KB of RAM. Peripheral func-
tions include 5 external interrupts (3 external interrupts in MN101EFAG0G(D)), including NMI, 10 timer
counters, 4 types of serial interfaces, A/D converter, watchdog timer and buzzer output. The system configuration
is suitable for system control microcontroller.
With 3 oscillation systems (internal frequency: 16 MHz, high-speed crystal/ceramic frequency: max. 10 MHz,
low-speed crystal/ceramic frequency: 32.768 kHz) contained on the chip, the system clock can be switched to
high-speed frequency input (NORMAL mode) or PLL input (PLL mode), or low-speed frequency input (SLOW
mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for
the system can be selected by switching its frequency ratio by programming. High speed mode has NORMAL
mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2),
and the double speed mode which is based on the clock not dividing fpll.
A machine cycle (minimum instruction execution time) in NORMAL mode is 200 ns when the original oscillation
fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the
same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (max-
imum).
Publication date: November 2014

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MN101EFA8/A7/A3/A2/G0 Series
8-bit Single-chip Microcontroller
PubNo. 216A8-015E
1.1.2 Product Summary
This manual describes the following model.
Table:1.1.1 Product Summary
Model
ROM Size RAM Size
Classification
Capacitive Touch
Detection Circuit
MN101EFA8G
MN101EFA8D
128 KB
64 KB
6 KB
4 KB
Flash EEPROM version
MN101EFA3G
MN101EFA3D
128 KB
64 KB
6 KB
4 KB
Flash EEPROM version
-
MN101EFA7G
MN101EFA7D
128 KB
64 KB
6 KB
4 KB
Flash EEPROM version
MN101EFA2G
MN101EFA2D
128 KB
64 KB
6 KB
4 KB
Flash EEPROM version
-
MN101EFG0G
MN101EFG0D
128 KB
64 KB
6 KB
4 KB
Flash EEPROM version
-
Package
80 Pin TQFP
80 Pin LQFP
64 Pin TQFP
64 Pin LQFP
56 Pin TQFP
Publication date: November 2014

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MN101EFA8/A7/A3/A2/G0 Series
8-bit Single-chip Microcontroller
PubNo. 216A8-015E
1.2 Hardware Functions
Feature
- Memory Capacity:
ROM 128 KB / 64 KB
RAM 6 KB / 4 KB
- Package:
MN101EFA8/A3 Series
80-Pin TQFP (12 mm 12 mm / 0.50 mm pitch, halogen free)
80-Pin LQFP (14 mm 14 mm / 0.65 mm pitch, halogen free)
MN101EFA7/A2 Series
64-Pin TQFP (10 mm 10 mm / 0.50 mm pitch, halogen free)
64-Pin LQFP (14 mm 14 mm / 0.80 mm pitch)
MN101EFG0 Series
56-Pin TQFP (10 mm 10 mm / 0.65 mm pitch, halogen free)
Panasonic "halogen free" semiconductor products refer to the products made of molding resin and
interposer which conform to the following standards.
- Bromine
: 900 ppm (Maximum Concentration Value)
- Chlorine
: 900 ppm (Maximum Concentration Value)
- Bromine + Chlorine : 1500 ppm (Maximum Concentration Value)
The above-mentioned standards are based on the numerical value described in IEC61249-2-21.
Antimony and its compounds are not added intentionally.
- Machine Cycle:
High-speed mode 0.05 s / 20 MHz (4.0 V to 5.5 V)
Low-speed mode 62.5 s / 32 kHz (4.0 V to 5.5 V)
- Oscillation circuit: 3 channel oscillation circuit
Internal oscillation (frc): 16 MHz
Crystal/ceramic (fosc): Maximum 10 MHz
Crystal/ceramic (fx): Maximum 32.768 kHz
-Clock Multiplication circuit (PLL Circuit)
PLL circuit output clock (fpll): fosc multiplied by 2, 3, 4, 5, 6, 8, 10,
1/2 frc multiplication by 4, 5 enable
-Clock Gear for System Clock
System Clock (fs): fpll divided by 1, 2, 4, 16, 32, 64, 128
-Clock Gear for control clock of peripheral function
Control clock of peripheral function (fpll-div): stop or fpll divided by 1, 2, 4, 8, 16
Publication date: November 2014