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1.1 Overview
MN101EF94 Series
8-bit Single-chip Microcontroller
PubNo. 21694-012E
1.1.1 Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series)
incorporate multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD,
LD, printer, telephone, home automation, pager, air conditioner, PPC, fax machine, music instrument and other
applications.
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim-
ple efficient instruction set. MN101EF94G has an internal 128 KB of ROM and 6 KB of RAM. MN101EF94F
has an internal 96 KB of ROM and 6 KB of RAM. Peripheral functions include 5 external interrupts, 29 internal
interrupts including NMI, 11 timer counters, 6 types of serial interfaces, A/D converter, LCD driver, 2 types of
watchdog timer, data automatic function and buzzer output. The system configuration is suitable for in camera,
timer selector for VCR, CD player, or minicomponent.
With 5 oscillation systems (high-speed (internal frequency: 20 MHz), high-speed (crystal/ceramic frequency:
max. 10 MHz) / low-speed (internal frequency: 30 kHz), low-speed (crystal/ceramic frequency: 32.768 kHz) and
PLL: frequency multiplier of high frequency) contained on the chip, the system clock can be switched to high-
speed frequency input (NORMAL mode), PLL input (PLL mode), or to low-speed frequency input (SLOW
mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for
the system can be selected by switching its frequency ratio by programming. High speed mode has the normal
mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2),
and the double speed mode which is based on the clock not dividing fpll.
A machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original oscillation
fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the
same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (max-
imum).
1.1.2 Product Summary
This manual describes the following model.
Table:1.1.1 Product Summary
Model
ROM Size RAM Size
Classification
Package
MN101EF94G
MN101EF94F
128 KB
96 KB
6 KB
6 KB
Flash EEPROM version 100 Pin LQFP
Publication date: February 2015

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Chapter 1
DataSheet
1.2 Hardware Functions
Feature
- ROM / RAM capacity:
MN101EF94G: ROM 128 KB / RAM 6 KB
MN101EF94F:ROM 96 KB / RAM 6 KB
- Package:
LQFP100-P-1414C (14 mm 14 mm / 0.5 mm pitch, halogen free)
Panasonic "halogen free" semiconductor products refer to the products made of molding resin and
interposer which conform to the following standards.
- Bromine : 900 ppm (Maximum Concentration Value)
- Chlorine : 900 ppm (Maximum Concentration Value)
- Bromine + Chlorine : 1500 ppm (Maximum Concentration Value)
The above-mentioned standards are based on the numerical value described in IEC61249-2-21.
Antimony and its compounds are not added intentionally.
- Machine Cycle:
NORMAL mode
0.05 s/ 20 MHz (2.7 V to 5.5 V)
0.125 s/ 8 MHz (1.8 V to 5.5 V)
SLOW mode
62.5 s/ 32 kHz (1.8 V to 5.5 V)
- Oscillation Circuit
High-speed (Internal oscillation: frc = 16MHz)
High-speed (External oscillation: fosc)
Low-speed (Internal oscillation: frcs = 32.5kHz)
Low-speed (External oscillation: fx)
- PLL:
PLL clock (fpll): fosc multiplied by 2, 3, 4, 5, 6, 8, 10
frc multiplied by 2, 2.5
- Memory Bank
Data area consists of memory banks 0 to 2 with each bank consisting of 64 KB.
- Operation Mode
NORMAL/SLOW/HALT/LP/STOP
- Operating Voltage: 1.8 V to 5.5 V
- Operation Ambient Temperature: -40 C to +85 C
- External Interrupts: 5
IRQ0/IRQ1/IRQ2/IRQ3/IRQ4
Hardware Functions
I-2

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MN101EF94 Series
8-bit Single-chip Microcontroller
PubNo. 21694-012E
- Timer Counter: 11
- General-purpose 8-bit timer 5
- General-purpose 16-bit timer 2
- Motor control 16-bit timer 1
- 8-bit free-run timer 1
- Time-base timer 1
- Baud rate timer 1
Timer 0 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), added pulse (2 bits) type PWM output, event count,
simple pulse width measurement
- Clock source
fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128,
fs/2, fs/4, fs/8, fslow, external clock, timer A output
- Real-time control
Timer (PWM) output is controlled among the three values: "Fixed to High", "Fixed to Low",
or "Hi-Z" at falling edge of external interrupt 0 (IRQ0)
Timer 1 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), event count
16-bit cascade connection (connected with timer 0)
- Clock source
fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128,
fs/2, fs/4, fs/8, fslow, external clock, timer A output
Timer 2 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), added pulse (2 bits) type PWM output, event count,
simple pulse width measurement,
24-bit cascade connection (connected with timer 0, 1), timer synchronous output
- Double-buffered compare register (1)
- Clock source
fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128,
fs/2, fs/4, fs/8, fslow, external clock, timer A output
- Real-time control
Timer (PWM) output is controlled among the three values: "Fixed to High", "Fixed to Low",
or "Hi-Z" at falling edge of external interrupt 0 (IRQ0)
Timer 3 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), event count
16-bit cascade connection (connected with timer 2),
32-bit cascade connection (connected with timer 0, 1, 2)
- Double-buffered compare register (1)
- Clock source
fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128,
fs/2, fs/4, fs/8, fslow, external clock, timer A output
Timer 4 (General-purpose 8-bit timer)
- Square wave output (Timer pulse output), added pulse (2-bit) type PWM output,
event count, simple pulse width measurement
- Clock source
fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128,
fs/2, fs/4, fs/8, fslow, external clock, timer A output
Publication date: February 2015