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8088
8-BIT HMOS MICROPROCESSOR
8088 8088-2
Y 8-Bit Data Bus Interface
Y 16-Bit Internal Architecture
Y Direct Addressing Capability to 1 Mbyte
of Memory
Y Direct Software Compatibility with 8086
CPU
Y 14-Word by 16-Bit Register Set with
Symmetrical Operations
Y 24 Operand Addressing Modes
Y Byte Word and Block Operations
Y 8-Bit and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
Y Two Clock Rates
5 MHz for 8088
8 MHz for 8088-2
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
The Intel 8088 is a high performance microprocessor implemented in N-channel depletion load silicon gate
technology (HMOS-II) and packaged in a 40-pin CERDIP package The processor has attributes of both 8-
and 16-bit microprocessors It is directly compatible with 8086 software and 8080 8085 hardware and periph-
erals
231456 – 1
Figure 1 8088 CPU Functional Block Diagram
231456 – 2
Figure 2 8088 Pin Configuration
August 1990
Order Number 231456-006

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8088
Table 1 Pin Description
The following pin function descriptions are for 8088 systems in either minimum or maximum mode The ‘‘local
bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to
additional bus buffers)
Symbol
Pin No Type
Name and Function
AD7 – AD0
9 – 16
I O ADDRESS DATA BUS These lines constitute the time multiplexed
memory IO address (T1) and data (T2 T3 Tw T4) bus These lines are
active HIGH and float to 3-state OFF during interrupt acknowledge and
local bus ‘‘hold acknowledge’’
A15 – A8
2–8 39 O ADDRESS BUS These lines provide address bits 8 through 15 for the
entire bus cycle (T1 – T4) These lines do not have to be latched by ALE
to remain valid A15 – A8 are active HIGH and float to 3-state OFF
during interrupt acknowledge and local bus ‘‘hold acknowledge’’
A19 S6 A18 S5 35–38
A17 S4 A16 S3
O ADDRESS STATUS During T1 these are the four most significant
address lines for memory operations During I O operations these lines
are LOW During memory and I O operations status information is
available on these lines during T2 T3 Tw and T4 S6 is always low
The status of the interrupt enable flag bit (S5) is updated at the
beginning of each clock cycle S4 and S3 are encoded as shown
This information indicates which segment register is presently being
used for data accessing
These lines float to 3-state OFF during local bus ‘‘hold acknowledge’’
S4 S3 Characteristics
0 (LOW)
0
1 (HIGH)
1
S6 is 0 (LOW)
0 Alternate Data
1 Stack
0 Code or None
1 Data
RD 32 O READ Read strobe indicates that the processor is performing a
memory or I O read cycle depending on the state of the IO M pin or
S2 This signal is used to read devices which reside on the 8088 local
bus RD is active LOW during T2 T3 and Tw of any read cycle and is
guaranteed to remain HIGH in T2 until the 8088 local bus has floated
This signal floats to 3-state OFF in ‘‘hold acknowledge’’
READY
22 I READY is the acknowledgement from the addressed memory or I O
device that it will complete the data transfer The RDY signal from
memory or I O is synchronized by the 8284 clock generator to form
READY This signal is active HIGH The 8088 READY input is not
synchronized Correct operation is not guaranteed if the set up and hold
times are not met
INTR
18 I INTERRUPT REQUEST is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation A
subroutine is vectored to via an interrupt vector lookup table located in
system memory It can be internally masked by software resetting the
interrupt enable bit INTR is internally synchronized This signal is active
HIGH
TEST
23 I TEST input is examined by the ‘‘wait for test’’ instruction If the TEST
input is LOW execution continues otherwise the processor waits in an
‘‘idle’’ state This input is synchronized internally during each clock
cycle on the leading edge of CLK
2

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8088
Symbol Pin No
NMI 17
RESET
21
CLK
VCC
GND
MN MX
19
40
1 20
33
Type
I
I
I
I
Table 1 Pin Description (Continued)
Name and Function
NON-MASKABLE INTERRUPT is an edge triggered input which causes a
type 2 interrupt A subroutine is vectored to via an interrupt vector lookup
table located in system memory NMI is not maskable internally by
software A transition from a LOW to HIGH initiates the interrupt at the end
of the current instruction This input is internally synchronized
RESET causes the processor to immediately terminate its present activity
The signal must be active HIGH for at least four clock cycles It restarts
execution as described in the instruction set description when RESET
returns LOW RESET is internally synchronized
CLOCK provides the basic timing for the processor and bus controller It is
asymmetric with a 33% duty cycle to provide optimized internal timing
VCC is the a5V g10% power supply pin
GND are the ground pins
MINIMUM MAXIMUM indicates what mode the processor is to operate in
The two modes are discussed in the following sections
The following pin function descriptions are for the 8088 minimum mode (i e MN MX e VCC) Only the pin
functions which are unique to minimum mode are described all other pin functions are as described above
Symbol Pin No Type
Name and Function
IO M
28 O STATUS LINE is an inverted maximum mode S2 It is used to distinguish a
memory access from an I O access IO M becomes valid in the T4 preceding a
bus cycle and remains valid until the final T4 of the cycle (I O e HIGH M e
LOW) IO M floats to 3-state OFF in local bus ‘‘hold acknowledge’’
WR 29 O WRITE strobe indicates that the processor is performing a write memory or write
I O cycle depending on the state of the IO M signal WR is active for T2 T3 and
Tw of any write cycle It is active LOW and floats to 3-state OFF in local bus
‘‘hold acknowledge’’
INTA
24 O INTA is used as a read strobe for interrupt acknowledge cycles It is active LOW
during T2 T3 and Tw of each interrupt acknowledge cycle
ALE 25 O ADDRESS LATCH ENABLE is provided by the processor to latch the address
into an address latch It is a HIGH pulse active during clock low of T1 of any bus
cycle Note that ALE is never floated
DT R
27 O DATA TRANSMIT RECEIVE is needed in a minimum system that desires to use
a data bus transceiver It is used to control the direction of data flow through the
transceiver Logically DT R is equivalent to S1 in the maximum mode and its
timing is the same as for IO M (T e HIGH R e LOW) This signal floats to
3-state OFF in local ‘‘hold acknowledge’’
DEN
26 O DATA ENABLE is provided as an output enable for the data bus transceiver in a
minimum system which uses the transceiver DEN is active LOW during each
memory and I O access and for INTA cycles For a read or INTA cycle it is
active from the middle of T2 until the middle of T4 while for a write cycle it is
active from the beginning of T2 until the middle of T4 DEN floats to 3-state OFF
during local bus ‘‘hold acknowledge’’
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