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AVAILABLE
DS1990A
Serial Number iButton
General Description
The DS1990A serial number iButton® is a rugged data
carrier that serves as an electronic registration number
for automatic identification. Data is transferred serially
through the 1-Wire® protocol, which requires only a sin-
gle data lead and a ground return. Every DS1990A is
factory lasered with a guaranteed unique 64-bit regis-
tration number that allows for absolute traceability. The
durable stainless-steel iButton package is highly resis-
tant to environmental hazards such as dirt, moisture,
and shock. Its compact coin-shaped profile is self-
aligning with mating receptacles, allowing the DS1990A
to be used easily by human operators. Accessories
enable the DS1990A iButton to be mounted on almost
any object, including containers, pallets, and bags.
Access Control
Work-In-Progress Tracking
Tool Management
Inventory Control
Applications
OOrrddeerriinngg IInnffoorrmmaattiioonn
PART
TEMP RANGE
PIN-PACKAGE
DS1990A-F5+
-40°C to +85°C
F5 iButton
DS1990A-F3+
-40°C to +85°C
F3 iButton
+Denotes a lead(Pb)-free/RoHS-compliant package.
Functional Diagrams
Examples of Accessories
PART
DS9096P
DS9101
DS9093RA
DS9093A
DS9092
ACCESSORY
Self-Stick Adhesive Pad
Multipurpose Clip
Mounting Lock Ring
Snap-In Fob
iButton Probe
Features
Can Be Read in Less Than 5ms
Operating Range: 2.8V to 6.0V, -40°C to +85°C
Common iButton Features
Unique Factory-Lasered 64-Bit Registration
Number Ensures Error-Free Device Selection and
Absolute Traceability Because No Two Parts are
Alike
Built-In Multidrop Controller for 1-Wire Net
Digital Identification by Momentary Contact
Data Can Be Accessed While Affixed to Object
Economically Communicates to Bus Master with
a Single Digital Signal at 16.3kbps
Button Shape is Self-Aligning with Cup-Shaped
Probes
Durable Stainless-Steel Case Engraved with
Registration Number Withstands Harsh
Environments
Easily Affixed with Self-Stick Adhesive Backing,
Latched by its Flange, or Locked with a Ring
Pressed Onto its Rim
Pin Configurations
F3 SIZE
3.10mm
0.51mm
F5 SIZE
5.89mm
0.51mm
BRANDING
u t t o n®. c
16.25mm
89 ® 01
000000FBC52B
W
W
1-Wire®
ZZZ DS1990A
17.35mm
IO
GND
IO
GND
iButton and 1-Wire are registered trademarks of Maxim
PIinnteCgorantfeigduPrarotidouncstsa,pInpce.ar at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
Rev: 10/08

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DS1990A
Serial Number iButton
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND .....................................-0.5V to +6.0V
IO Sink Current....................................................................20mA
Junction Temperature ......................................................+125°C
Storage Temperature Range .............................-55°C to +125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
VPUP (Notes 1, 2)
1-Wire Pullup Resistance
RPUP (Notes 3, 4)
Input Capacitance
CIO (Notes 5, 6)
Input Load Current
IL (Note 7)
Input Low Voltage
VIL (Notes 1, 3, 8)
Input High Voltage
VIH (Notes 1, 9)
Output Low Voltage at 4mA
VOL (Note 1)
Operating Charge
QOP (Notes 6, 10)
Recovery Time
tREC (Note 3)
Time Slot Duration
tSLOT (Note 3)
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
2.8 6.0
0.6 5
100 800
0.25
0.3
2.2
0.4
30
1
61
V
k
pF
μA
V
V
V
nC
μs
μs
Reset Low Time
Reset High Time
Presence-Detect High Time
Presence-Detect Low Time
Presence-Detect Sample Time
IO PIN: 1-Wire WRITE
tRSTL
tRSTH
tPDH
tPDL
tMSP
(Notes 3, 11)
(Notes 3, 12)
(Note 13)
(Note 3)
480 μs
480 μs
15 60 μs
60 240 μs
60 75 μs
Write-Zero Low Time
Write-One Low Time
IO PIN: 1-Wire READ
tW0L
tW1L
(Notes 3, 14)
(Notes 3, 14)
60 120 μs
1 15 μs
Read Low Time
Read Sample Time
tRL
tMSR
(Notes 3, 15)
(Notes 3, 15)
1
tRL + 
15 - 
15
μs
μs
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
All voltages are referenced to ground.
External pullup voltage. See Figure 4.
System requirement.
Full RPUP range is guaranteed by design and simulation and not production tested. Production testing performed at a
fixed RPUP value. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-
Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recov-
ery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required.
Capacitance on the IO pin could be 800pF when power is first applied. If a 5kΩ resistor is used to pull up the IO line to
VPUP, 5µs after power has been applied the parasite capacitance will not affect normal communications.
Guaranteed by design, simulation only. Not production tested.
Input load is to ground.
2 Maxim Integrated

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DS1990A
Serial Number iButton
Note 8: The voltage on IO must be less than or equal to VILMAX whenever the master drives the line low.
Note 9: VIH is a function of the internal supply voltage.
Note 10: 30nC per 72 time slots at 5.0V pullup voltage with a 5kΩ pullup resistor and tSLOT 120µs.
Note 11: The reset low time (tRSTL) should be restricted to a maximum of 960µs to allow interrupt signaling. A longer duration could
mask or conceal interrupt pulses if this device is used in parallel with a DS1994.
Note 12: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 13: Presence pulse is guaranteed only after a preceding reset pulse (tRSTL).
Note 14: ε in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 15: δ in Figure 7 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
iButton CAN PHYSICAL SPECIFICATION
SIZE
WEIGHT (DS1990A)
See the Package Information section.
Ca. 2.5 grams
Detailed Description
The block diagram in Figure 1 shows the major function
blocks of the device. The DS1990A takes the energy it
needs to operate from the IO line, as indicated by the
parasite power block. The ROM function control unit
includes the 1-Wire interface and the logic to implement
the ROM function commands, which access 64 bits of
lasered ROM.
DS1990A
PARASITE POWER
IO
Figure 1. Block Diagram
ROM
FUNCTION CONTROL
64-BIT
LASERED ROM
Maxim Integrated
3

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DS1990A
Serial Number iButton
64-Bit Lasered ROM
Each DS1990A contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a CRC of the first 56 bits. See Figure 2 for details.
The 1-Wire CRC is generated using a polynomial gen-
erator consisting of a shift register and XOR gates as
shown in Figure 3. The polynomial is X8 + X5 + X4 + 1.
Additional information about the 1-Wire Cyclic
Redundancy Check (CRC) is available in Application
Note 27: Understanding and Using Cyclic Redundancy
Checks with Maxim iButton Products.
The shift register bits are initialized to 0. Then starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the 48th bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of CRC returns the shift register to all 0s.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS1990A
is a slave device. The bus master is typically a micro-
controller or PC. For small configurations, the 1-Wire
communication signals can be generated under soft-
ware control using a single port pin. Alternatively, the
DS2480B 1-Wire line driver chip or serial-port adapters
based on this chip (DS9097U series) can be used. This
simplifies the hardware design and frees the micro-
processor from responding in real time. The discussion
of this bus system is broken down into three topics:
hardware configuration, transaction sequence, and
1-Wire signaling (signal types and timing). The 1-Wire
protocol defines bus transactions in terms of the bus
state during specific time slots that are initiated on the
falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of
the Book of iButton Standards.
MSB
8-BIT
CRC CODE
MSB LSB MSB
Figure 2. 64-Bit Lasered ROM
48-BIT SERIAL NUMBER
LSB
8-BIT FAMILY CODE
(01h)
LSB MSB
LSB
POLYNOMIAL = X8 + X5 + X4 + 1
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
X0 X1 X2 X3
Figure 3. 1-Wire CRC Generator
5TH
STAGE
X4
6TH
STAGE
7TH
STAGE
8TH
STAGE
X5 X6 X7 X8
INPUT DATA
4 Maxim Integrated

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DS1990A
Serial Number iButton
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS1990A is
open drain with an internal circuit equivalent to that
shown in Figure 4. A multidrop bus consists of a 1-Wire
bus with multiple slaves attached. At standard speed,
the 1-Wire bus has a maximum data rate of 16.3kbps.
The value of the pullup resistor primarily depends on
the network size and load conditions. For most applica-
tions, the optimal value of the pullup resistor is approxi-
mately 2.2kΩ. The idle state for the 1-Wire bus is high.
If for any reason a transaction needs to be suspended,
the bus must be left in the idle state if the transaction is
to resume. If this does not occur and the bus is left low
for more than 120µs, one or more devices on the bus
may be reset.
Transaction Sequence
The protocol for accessing the DS1990A through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
Initialization
All transactions on the 1-Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s). The
presence pulse lets the bus master know that the
DS1990A is on the bus and is ready to operate. For
more details, see the 1-Wire Signaling section.
SIMPLE BUS MASTER
Rx
Tx
OPEN-DRAIN
PORT PIN
VPUP
RPUP
Rx = RECEIVE
Tx = TRANSMIT
DS1990A 1-Wire PORT
DATA
Rx
Tx
100Ω MOSFET
DS2480B BUS MASTER
HOST CPU
SERIAL
PORT
SERIAL IN
SERIAL OUT
VDD
POL
RXD
TXD
VPP
1-W
N.C.
GND
Figure 4. Hardware Configuration
DS2480B
+5V
TO 1-Wire DATA
Maxim Integrated
5