ATF1508AZ.pdf 데이터시트 (총 22 페이지) - 파일 다운로드 ATF1508AZ 데이타시트 다운로드

No Preview Available !

Features
High Density, High Performance Electrically Erasable Complex
Programmable Logic Device
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 68, 84, 100, 160-pins
– 7.5 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 125 MHz
– Enhanced Routing Resources
Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register within a COM output
Advanced Power Management Features
– Automatic 100 µA Stand-By for “Z” Version (Max.)
– Pin-Controlled 100 µA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 84-pin PLCC and 100-pin PQFP and TQFP and
160-pin PQFP Packages
Advanced Flash Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
3.3 or 5.0V I/O pins
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D - Latch Mode
Combinatorial Output with Registered Feedback within any Macrocell
Three Global Clock Pins
ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-Keeper” Option
VCC Power-Up Reset Option
Pull-Up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge Controlled Power Down “Z”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
High
Performance
E2 PLD
ATF1508AS/Z
Rev. 0784C–4/98
1

No Preview Available !

84-Lead PLCC
Top View
100-Lead TQFP
Top View
I/O/PD1
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74 I/O
73 I/O
72 GND
71 I/O/TDO
70 I/O
69 I/O
68 I/O
67 I/O
66 VCCIO
65 I/O
64 I/O
63 I/O
62 I/O/TCK
61 I/O
60 I/O
59 GND
58 I/O
57 I/O
56 I/O
55 I/O
54 I/O
100-Lead PQFP
Top View
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
160-Lead PQFP
Top View
75 I/O
74 GND
73 I/O/TDO
72 I/O
71 I/O
70 I/O
69 I/O
68 I/O
67 I/O
66 VCCIO
65 I/O
64 I/O
63 I/O
62 I/O/TCK
61 I/O
60 I/O
59 GND
58 I/O
57 I/O
56 I/O
55 I/O
54 I/O
53 I/O
52 I/O
51 VCCIO
I/O
I/O
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 I/O
79 I/O
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 I/O
73 I/O
72 I/O
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 I/O
56 I/O
55 I/O
54 I/O
53 VCCIO
52 I/O
51 I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O/TMS
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120 N/C
119 N/C
118 N/C
117 N/C
116 N/C
115 N/C
114 N/C
113 GND
112 I/O/TDO
111 I/O
110 I/O
109 I/O
108 I/O
107 I/O
106 I/O
105 I/O
104 VCCIO
103 I/O
102 I/O
101 I/O
100 I/O
99 I/O/TCK
98 I/O
97 I/O
96 I/O
95 GND
94 I/O
93 I/O
92 I/O
91 I/O
90 I/O
89 I/O
88 I/O
87 N/C
86 N/C
85 N/C
84 N/C
83 N/C
82 N/C
81 N/C
2 ATF1508AS/Z

No Preview Available !

Block Diagram
6 to 12
ATF1508AS/Z
3

No Preview Available !

Description
The ATF1508AS is a high performance, high density Com-
plex Programmable Logic Device (CPLD) which utilizes
Atmel’s proven electrically erasable Flash memory technol-
ogy. With 128 logic macrocells and up to 100 inputs, it eas-
ily integrates logic from several TTL, SSI, MSI, LSI and
classic PLDs. The ATF1508AS’s enhanced routing switch
matrices increase usable gate count, and increase odds of
successful pin-locked design modifications.
The ATF1508AS has up to 96 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack-
age selected. Each dedicated pin can also serve as a glo-
bal control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Cascade logic between macrocells
in the ATF1508AS allows fast, efficient generation of com-
plex logic functions. The ATF1508AS contains eight such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms
The ATF1508AS macrocell, shown in Figure 1, is flexible
enough to support highly complex logic functions operating
at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select and
enable; and logic array inputs.
Unused Macrocells are automatically disabled by the com-
piler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1508AS. Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.
The ATF1508AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
Product Terms and Select MUX
Each ATF1508AS macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1508AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with a very small additional
delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
Flip Flop
The ATF1508AS’s flip flop has very flexible data and con-
trol functions. The data input can come from either the
XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows cre-
ation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and
SR operation, the flip flop can also be configured as a flow-
through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The clock itself can either be the Global CLK Signal (GCK)
or an individual product term. The flip flop changes state on
the clock's rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be
selected as a clock enable. When the clock enable function
is active and the enable signal (product term) is low, all
clock edges are ignored. The flip flop’s asynchronous reset
signal (AR) can be either the Global Clear (GCLEAR), a
product term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous preset
(AP) can be a product term or always off.
Output Select and Enable
The ATF1508AS macrocell output can be selected as reg-
istered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
4 ATF1508AS/Z

No Preview Available !

ATF1508AS/Z
ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can be selected as
one of the global OUTPUT enable signals. The device has
six global OE signals.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 128 macrocells.
The Switch Matrix in each Logic Block receives as its inputs
all signals from the global bus. Under software control, up
to 40 of these signals can be selected as inputs to the
Logic Block.
Foldback Bus
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each
region allows generation of high fan-in sum terms (up to 21
product terms) with a small additional delay.
3.3V or 5.0V I/O Operation
The ATF1508AS device has two sets of VCC pins viz,
VCCINT and VCCIO. VCCINT pins must always be connected to
a 5.0V power supply. VCCINT pins are for input buffers and
are “compatible” with both 3.3V and 5.0V inputs. VCCIO pins
are for I/O output drives and can be connected for 3.3/5.0V
power supply.
Open-Collector Output Option
This option enables the device output to provide control
signals such as an interrupt that can be asserted by any of
the several devices.
5