INA-32063.pdf 데이터시트 (총 10 페이지) - 파일 다운로드 INA-32063 데이타시트 다운로드

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3.0 GHz Wideband Silicon
RFIC Amplifier
Technical Data
INA-32063
Features
• 17 dB Gain at 1.9 GHz
• +3 dBm P1 dB at 1.9 GHz
• Single +3V Supply
• Unconditionally Stable
Applications
• LO Buffer and Driver
Amplifier for Cellular,
Cordless, Special Mobile
Radio, PCS, ISM, Wireless
LAN, DBS, TVRO, and TV
Tuner
Simplified Schematic
Surface Mount SOT-363
(SC-70) Package
Pin Connections and
Package Marking
GND 2 1
GND 1 2
INPUT 3
6 OUTPUT
& Vd
5 GND 1
4 Vd
Note: Package marking provides
orientation and identification.
Vd
Output & Vd
Description
Hewlett-Packard’s INA-32063 is a
Silicon RFIC amplifier that offers
excellent gain and output power
for applications to 3.0 GHz.
Packaged in an ultraminiature
SOT-363 package, it requires half
of the board space of a SOT-143
package.
The INA-32063 offers wide
bandwidth and good linearity and
17 dB gain with a modest supply
current. With its input and output
matched internally to 50 , the
INA-32063 is a simple to use gain
block that is suitable for
numerous applications.
The INA-32063 is fabricated using
HP’s 30 GHz – fmax, ISOSAT™
Silicon-bipolar process that uses
nitride, self-alignment,
submicrometer lithography,
trench isolation, ion implantation,
and polyimide intermetal dielec-
tric and scratch protection to
achieve superior performance,
uniformity and reliability.
Input
Gnd1
Gnd2

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2
Absolute Maximum Ratings
Symbol
Vd
Pin
Tj
TSTG
Parameter
Device Voltage,
RF output to ground
CW RF Input Power
Junction Temperature
Storage Temperature
Units
V
Absolute
Maximum[1]
6.0
dBm
°C
°C
+7.0
150
-65 to 150
Thermal Resistance[2]:
θjc = 170°C/W
Notes:
1. Operation of this device above any one
of these limits may cause permanent
damage.
2. TC = 25°C (TC is defined to be the
temperature at the package pins where
contact is made to the circuit board)
INA-32063 Electrical Specifications, TC = 25°C, ZO = 50 ,Vd = 3 V
Symbol
Parameters and Test Conditions
Units Min. Typ. Max. Std.
Dev.[4]
|S 21|2
Gain in 50 system
f = 0.9 GHz dB
16.8
f = 1.9 GHz
15.5[3] 17.8
f = 2.4 GHz
18.2
0.39
NF50
P1dB
Noise Figure
Output Power at 1 dB Gain Compression
f = 1.9 GHz
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
dB
dBm
4.4 0.21
3.6
4.8
4.0
IP3 Output Third Order Intercept Point
f = 0.9 GHz dBm
f = 1.9 GHz
f = 2.4 GHz
15.3
14.4
11.5
VSWRin
VSWRout
Ιd
Input VSWR
Output VSWR
Device Current
f = 0.1 – 2.4 GHz
f = 0.1 – 2.4 GHz
mA
1.1:1
1.6:1
20
25[3]
1.1
Notes:
3. Guaranteed specifications are 100% tested in production.
4. Standard deviation number is based on measurement of a large number of parts from three non-consecutive wafer lots
during the initial characterization of this product, and is intended to be used as an estimate for distribution of the
typical specification.

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3
INA-32063 Typical Performance, TC = 25°C, ZO = 50 , Vd = 3 V
25 6
2.7 V
3.0 V
5.5 3.3 V
20
8
6
2.7 V
3.0 V
3.3 V
5
15
4.5
4
2
10
2.7 V
3.0 V
3.3 V
5
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 1. Gain vs. Frequency and
Voltage.
4
3.5
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 2. Noise Figure vs. Frequency
and Voltage.
0
-2
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 3. Output Power for 1 dB Gain
Compression vs. Frequency and
Voltage.
25
20
15
10
-40°C
+25°C
+85°C
5
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 4. Gain vs. Frequency and
Temperature.
6.5
-40°C
6 +25°C
+85°C
5.5
5
4.5
4
3.5
3
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 5. Noise Figure vs. Frequency
and Temperature.
8
-40°C
+25°C
6 +85°C
4
2
0
-2
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 6. Output Power for 1 dB Gain
Compression vs. Frequency and
Temperature.
43
2.5
2
1.5
1
0.5 VSWR in
VSWR out
0
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 7. Input and Output VSWR vs.
Frequency.
35
-40°C
30 +25°C
+85°C
25
20
15
10
5
0
01 23 4 5
Vd (V)
Figure 8. Supply Current vs. Voltage
and Temperature.
18
16
14
12
10
-40°C
8 +25°C
+85°C
6
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)
Figure 9. Third Order Intercept
Point, IP3 vs. Frequency and
Temperature.

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4
INA-32063 Typical Scattering Parameters[5], TC = 25°C, ZO = 50 ,Vd = 3.0 V
Freq.
GHz
S11
Mag Ang
dB
S21
Mag
Ang dB
S12
Mag Ang
S22
Mag Ang
0.1
0.034 19 16.5
6.72
-4 -26.8 0.046
3
0.215
-5
0.2
0.034 30 16.5
6.71
-9 -27.9 0.040
0
0.230
-6
0.3
0.039 35 16.6
6.73 -13 -27.7 0.041 -3
0.227
-7
0.4
0.043 41 16.6
6.75 -17 -28.3 0.039 -10
0.238
-8
0.5
0.053 53 16.6
6.78 -22 -28.3 0.038 -7
0.226
-8
0.6
0.054 49 16.7
6.80 -26 -28.0 0.040 -10
0.218
-9
0.7
0.059 49 16.7
6.85 -30 -28.5 0.038 -12
0.223 -12
0.8
0.065 50 16.8
6.90 -35 -28.9 0.036 -13
0.224 -16
0.9
0.072 49 16.8
6.94 -39 -29.1 0.035 -12
0.220 -21
1.0
0.080 47 16.9
7.00 -44 -29.2 0.035 -11
0.215 -25
1.1
0.084 48 17.0
7.09 -48 -29.1 0.035 -13
0.211 -29
1.2
0.090 46 17.1
7.16 -53 -29.3 0.034 -15
0.211 -33
1.3
0.096 45 17.2
7.23 -58 -29.5 0.033 -15
0.206 -40
1.4
0.101 46 17.3
7.32 -62 -29.8 0.033 -15
0.205 -47
1.5
0.107 45 17.4
7.40 -67 -29.9 0.032 -14
0.204 -55
1.6
0.109 43 17.5
7.48 -72 -29.6 0.033 -16
0.194 -63
1.7
0.108 41 17.6
7.59 -77 -29.9 0.032 -19
0.193 -68
1.8
0.110 38 17.7
7.69 -83 -30.1 0.031 -20
0.194 -77
1.9
0.113 36 17.8
7.79 -88 -30.5 0.030 -22
0.197 -85
2.0
0.118 32 17.9
7.88 -94 -30.6 0.029 -23
0.198 -94
2.1
0.121 26 18.0
7.98 -100 -30.8 0.029 -25
0.206 -101
2.2
0.129 20 18.1
8.03 -106 -31.1 0.028 -27
0.214 -111
2.3
0.138 13 18.1
8.06 -112 -31.3 0.027 -29
0.220 -120
2.4
0.151
6 18.2
8.09 -119 -31.5 0.027 -31
0.225 -128
2.5
0.163
-1 18.2
8.09 -125 -31.6 0.026 -34
0.232 -135
2.6
0.175
-7 18.1
8.04 -132 -32.0 0.025 -37
0.242 -143
2.7
0.189 -13 18.0
7.96 -138 -32.3 0.024 -42
0.247 -151
2.8
0.199 -19 17.9
7.84 -145 -32.8 0.023 -46
0.250 -160
2.9
0.208 -26 17.8
7.73 -152 -33.3 0.022 -51
0.250 -166
3.0
0.216 -33 17.6
7.56 -158 -33.6 0.021 -56
0.249 -173
3.1
0.224 -40 17.3
7.36 -165 -34.2 0.019 -63
0.246 180
3.2
0.234 -48 17.1
7.16 -171 -35.1 0.018 -70
0.239 173
3.3
0.243 -57 16.8
6.92 -177 -35.8 0.016 -78
0.229 168
3.4
0.254 -64 16.5
6.67 176 -36.7 0.015 -86
0.220 163
3.5
0.266 -71 16.1
6.39 170 -37.1 0.014 -97
0.212 157
3.6
0.280 -77 15.8
6.13 165 -38.3 0.012 -110
0.196 151
3.7
0.292 -83 15.4
5.86 159 -38.8 0.011 -121
0.182 146
3.8
0.301 -88 14.9
5.58 154 -39.0 0.011 -130
0.170 142
3.9
0.309 -92 14.5
5.32 149 -38.3 0.012 -142
0.156 136
4.0
0.317 -97 14.1
5.07 144 -37.6 0.013 -152
0.139 131
4.1
0.323 -101 13.7
4.84 139 -36.5 0.015 -160
0.124 125
4.2
0.327 -105 13.3
4.61 134 -35.3 0.017 -166
0.110 120
4.3
0.328 -109 12.9
4.39 130 -34.0 0.020 -173
0.095 112
4.4
0.331 -113 12.4
4.19 126 -32.8 0.023 -178
0.079 101
4.5
0.333 -117 12.0
3.99 122 -31.7 0.026 177
0.065 88
4.6
0.334 -122 11.6
3.81 118 -30.7 0.029 172
0.052 68
4.7
0.337 -126 11.2
3.63 114 -29.8 0.032 168
0.041 42
4.8
0.338 -130 10.8
3.47 110 -29.0 0.036 165
0.031 15
4.9
0.342 -134 10.4
3.31 106 -28.0 0.040 162
0.022
-5
5.0
0.347 -137 10.0
3.17 103 -27.2 0.044 159
0.013 -17
Note:
5. Reference plane per Figure 15 in Applications Information section.
K
Factor
1.68
1.89
1.84
1.91
1.96
1.87
1.94
2.02
2.05
2.03
2.06
2.10
2.07
2.10
2.11
2.04
2.07
2.10
2.13
2.17
2.13
2.17
2.22
2.20
2.26
2.33
2.42
2.53
2.67
2.84
3.20
3.46
4.02
4.44
4.95
6.00
6.84
7.18
6.90
6.69
6.08
5.64
5.05
4.61
4.30
4.04
3.85
3.59
3.39
3.22

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5
INA-32063 Applications
Information
Introduction
The INA-32063 is a +3 volt silicon
RFIC amplifier that is designed
with a two stage internal network
to provide a broadband gain and
50 input and output impedance.
With a typical +4.8 dBm P-1 dB
compressed output power at
1900 MHz, for only 20 mA supply
current. The broad bandwidth,
INA-32063, is well suited for
amplifier applications in mobile
communication systems.
A feature of the INA-32063 is a
positive gain slope over the
1–2.5 GHz range that is useful in
many satellite-based TV and
datacom systems.
In addition to use in buffer and
driver amplifier applications in
the cellular market, the
INA-32063 will find many
applications in battery operated
wireless communication systems.
Operating Details
The INA-32063 is a voltage-biased
device that operates from a
+3 volt power supply with a
typical current drain of 20 mA. All
bias regulation circuitry is
integrated into the RFIC.
Figure 10 shows a typical imple-
mentation of the INA-32063. The
supply voltage for the INA-32063
must be applied to two terminals,
the Vd pin and the RF Output pin.
Gnd2
Gnd1
Gnd1
Cout
RF
Output
RFC
RF
Input
Cblock
Vd
Cbypass
Figure 10. Basic Amplifier
Application.
The Vd connection to the ampli-
fier is RF bypassed by placing a
capacitor to ground near the Vd
pin of the amplifier package.
The power supply connection to
the RF Output pin is achieved by
means of a RF choke (inductor).
The value of the RF choke must
be large relative to 50 in order
to prevent loading of the RF
Output. The supply voltage end of
the RF choke is bypassed to
ground with a capacitor. If the
physical layout permits, this can
be the same bypass capacitor that
is used at the Vd terminal of the
amplifier.
Blocking capacitors are normally
placed in series with the RF Input
and the RF Output to isolate the
DC voltages on these pins from
circuits adjacent to the amplifier.
The values for the blocking and
bypass capacitors are selected to
provide a reactance at the lowest
frequency of operation that is
small relative to 50 .
Example Layout for 50
Output Amplifier
An example layout for an ampli-
fier using the INA-32063 with
50 input and 50 output is
shown in Figure 11.
Gnd 1
RF Input
50
Gnd 2
50
Gnd 1
RF Output
and Vd
Figure 11. RF Layout.
This example uses a
microstripline design (solid
groundplane on the backside of
the circuit board). The circuit
board material is 0.031-inch thick
FR-4. Plated through holes (vias)
are used to bring the ground to
the topside of the circuit where
needed. The performance of
INA-32063 is sensitive to ground
path inductance. The two-stage
design creates the possibility of a
feedback loop being formed
through the ground returns of the
stages, Gnd 1 and Gnd 2.
Gnd 1
Gnd 2
VIA
Figure 12. INA-32063 Potential
Ground Loop.
Gnd 1
VIA
Gnd 2
VIA
Figure 13. INA-32063 Suggested
Layout.
At least one ground via should be
placed adjacent to each ground
pin to assure good RF grounding.
Multiple vias are used to reduce
the inductance of the path to
ground and should be placed as
close to the package terminals as
practical.
The effects of the potential
ground loop shown in Figure 12
may be observed as a “peaking” in
the gain versus frequency
response, an increase in input
VSWR, or even as return gain at
the input of the INA-32063.
Figure 14 shows an assembled
amplifier. The +3 volt supply is
fed directly into the Vd pin of the