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Philips Semiconductors
N-channel enhancement mode
TrenchMOStransistor
Product specification
BSP100
FEATURES
’Trench’ technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 30 V
ID = 6 A
RDS(ON) 100 m(VGS = 10 V)
RDS(ON) 200 m(VGS = 4.5 V)
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect transistor in a plastic
envelope
using
trench
technology.
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
The BSP100 is supplied in the
SOT223 surface mounting
package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
SOT223
4
123
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 k
Tsp = 25 ˚C
Tsp = 100 ˚C
Tamb = 25 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 65
MAX.
30
30
± 20
61
4.4
3.2
24
8.3
150
UNIT
V
V
V
A
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
Rth j-sp
Rth j-amb
PARAMETER
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
CONDITIONS
surface mounted, FR4
board
surface mounted, FR4
board
TYP.
12
70
MAX.
15
-
UNIT
K/W
K/W
1 Continuous current rating limited by package
February 1999
1
Rev 1.000

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Philips Semiconductors
N-channel enhancement mode
TrenchMOStransistor
Product specification
BSP100
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 6 A;
energy
tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD 15 V; RGS = 50 ; VGS = 10 V
IAS Non-repetitive avalanche
current
MIN.
-
MAX.
23
UNIT
mJ
- 6A
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
RDS(ON)
gfs
ID(ON)
IDSS
IGSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ls
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
On-state drain current
Zero gate voltage drain
current
Gate source leakage current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 10 µA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
VGS = 10 V; ID = 2.2 A
VGS = 4.5 V; ID = 1 A
VGS = 10 V; ID = 2.2 A; Tj = 150˚C
VDS = 20 V; ID = 2.2 A
VGS = 10 V; VDS = 1 V;
VGS = 4.5 V; VDS = 5 V
VDS = 24 V; VGS = 0 V;
VDS = 24 V; VGS = 0 V; Tj = 150˚C
VGS = ±20 V; VDS = 0 V
ID = 2.3 A; VDD = 15 V; VGS = 10 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 20 V; RD = 18 ;
VGS = 10 V; RG = 6
Resistive load
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
MIN. TYP. MAX. UNIT
30 -
-V
27 -
-V
1 2 2.8 V
0.4 -
-V
- 3.2 V
- 80 100 m
- 120 200 m
- - 170 m
2 4.5 -
S
3.5 -
-A
2- -A
- 10 100 nA
- 0.6 10 µA
- 10 100 nA
- 6 - nC
- 0.7 - nC
- 0.7 - nC
- 6 - ns
- 8 - ns
- 21 - ns
- 15 - ns
- 2.5 - nH
- 5 - nH
- 250 -
- 88 -
- 54 -
pF
pF
pF
February 1999
2
Rev 1.000

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Philips Semiconductors
N-channel enhancement mode
TrenchMOStransistor
Product specification
BSP100
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
IS Continuous source current Tsp = 25 ˚C
(body diode)
ISM Pulsed source current (body
diode)
VSD Diode forward voltage
IF = 1.25 A; VGS = 0 V
trr
Reverse recovery time
IF = 1.25 A; -dIF/dt = 100 A/µs;
Qrr Reverse recovery charge VGS = 0 V; VR = 25 V
MIN. TYP. MAX. UNIT
- - 6A
- - 24 A
- 0.82 1.2 V
- 69 - ns
- 55 - nC
120 PD%
110
Normalised Power Derating
100
90
80
70
60
50
40
30
20
10
0
0
20 40 60 80 100 120 140
Tsp / C
Fig.1. Normalised power dissipation.
PD% = 100PD/PD 25 ˚C = f(Tsp)
120 ID%
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tsp / C
Fig.2. Normalised continuous drain current.
ID% = 100ID/ID 25 ˚C = f(Tsp); conditions: VGS 10 V
Peak Pulsed Drain Current, IDM (A)
100
RDS(on) = VDS/ ID
10
1 d.c.
BSP100
tp = 10 us
100 us
1 ms
10 ms
100 ms
0.1
1
10
Drain-Source Voltage, VDS (V)
100
Fig.3. Safe operating area. Tsp = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Peak Pulsed Drain Current, IDM (A)
100
BSP100
10 D = 0.5
0.2
1 0.1
0.05
0.1 0.02
PD tp D = tp/T
0.01
1E-06
single pulse
T
1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Fig.4. Transient thermal impedance.
Zth j-sp = f(t); parameter D = tp/T
February 1999
3
Rev 1.000

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Philips Semiconductors
N-channel enhancement mode
TrenchMOStransistor
Product specification
BSP100
Drain Current, ID (A)
10
9 VGS = 20 V
10 V
5V
8
Tj = 25 C
7
6
5
4
3
2
1
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Drain-Source Voltage, VDS (V)
4.2 V
4V
3.8 V
3.6 V
3.4 V
3.2 V
1.8 2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Drain-Source On Resistance, RDS(on) (Ohms)
0.5
3.2 V 3.6 V 3.8V 4 V 4.2 V
3.4 V
0.4
Tj = 25 C
0.3
0.2 VGS =5 V
10V
0.1
20V
0
0 1 2 3 4 5 6 7 8 9 10
Drain Current, ID (A)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Drain current, ID (A)
10
9 VDS > ID X RDS(ON)
8
7 Tj = 25 C
6 150 C
5
4
3
2
1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
Transconductance, gfs (S)
6
5
Tj = 25 C
4
150 C
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID) ; parameter Tj
a
2
SOT223 30V Trench Normalised RDS(ON) = f(Tj)
1.5
1
0.5
0
-50 0
50 100 150
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
VGS(TO) / V
4
3 max.
typ.
2
1 min.
0
-60 -40 -20 0
20 40 60 80 100 120 140
Tj / C
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
February 1999
4
Rev 1.000

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Philips Semiconductors
N-channel enhancement mode
TrenchMOStransistor
Product specification
BSP100
1E-01
Sub-Threshold Conduction
1E-02
1E-03
min typ max
1E-04
1E-05
1E-06
01234
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
5
Capacitances, Ciss, Coss, Crss (pF)
1000
100
Ciss
Coss
Crss
10
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Source-Drain Diode Current, IF (A)
10
9 VGS = 0 V
8
7
6 150 C
5
4 Tj = 25 C
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A)
10
BSP100
25 C
Tj prior to avalanche =125 C
1
VDS
tp
ID
0.1
1E-06
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Gate-source voltage, VGS (V)
15
14 ID = 2.3A
13
12
Tj = 25 C
11 VDD = 15 V
10
9
8
7
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
February 1999
5
Rev 1.000