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APPLICATION NOTE
A V A I LABLE
AN76 • AN78 • AN81 • AN87
64K/32K/16K
X24F064/032/016
8K/4K/2K x 8 Bit
SerialFlashMemory with Block LockProtection
FEATURES
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
• Low Power CMOS
—Active read current less than 1mA
—Active program current less than 3mA
—Standby current less than 1µA
• Internally Organized 8K/4K/2K x 8
• New Programmable Block Lock Protection
—Software write protection
—Programmable hardware write protect
• Block Lock (0, 1/4, 1/2, or all of the Flash Memory
Array)
• 2 Wire Serial Interface
• Bidirectional Data Transfer Protocol
• 32 Byte Sector Programming
• Self Timed Program Cycle
—Typical programming time of 5ms per sector
• High Reliability
—Endurance: 100,000 cycles per byte
—Data retention: 100 years
• Available Packages
—8-lead PDIP
—8-lead SOIC (JEDEC)
—14-lead TSSOP (X24F032/016)
—20-lead TSSOP (X24F064)
DESCRIPTION
The X24F064/032/016 is a CMOS SerialFlash Memory
Family, internally organized 8K/4K/2K x 8. The family
features a serial interface and software protocol allow-
ing operation on a simple two wire bus.
Device select inputs (S0, S1, S2) allow up to eight
devices to share a common two wire bus.
A Program Protect Register accessed at the highest
address location, provides three new programming pro-
tection features: Software Programming Protection, Block
Lock Protection, and Hardware Programming Protection.
The Software Programming Protection feature prevents
any nonvolatile writes to the device until the WEL bit in
the program protect register is set. The Block LockTM Pro-
tection feature allows the user to individually protect four
blocks of the array by programming two bits in the pro-
gramming protect register. The Programmable Hardware
Program Protect feature allows the user to install each
device with PP tied to VCC, program the entire memory
array in place, and then enable the hardware program-
ming protection by programming a PPEN bit in the pro-
gram protect register. After this, selected blocks of the
array, including the program protect register itself, are
permanently protected from being programmed.
Xicor SerialFlash Memories are designed and tested for
applications requiring extended endurance. Inherent
data retention is greater than 100 years.
BLOCK DIAGRAM
SDA
Data Register
Sector Decode Logic
SCL
S0/S0
S1/S1
S2/S2
Command
Decode
and
Control Logic
X
Decode
Logic
Program
Protect
Register
32 8
Sectored
Memory
Array
PP
SerialFlashMemory and Block Lock
Protection are trademarks of Xicor, Inc.
©Xicor, Inc. 2000 Patents Pending
6686-3.8 10/27/00 EP
Programming Control Logic
High Voltage
Control
Characteristics subject to change without notice. 1 of 17

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X24F064/032/016
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the pull-up
resistor selection graph at the end of this data sheet.
Device Select (S0, S0, S1, S1, S2, S2)
The device select inputs are used to set the device
select bits of the 8-bit slave address. This allows multi-
ple devices to share a common bus. These inputs can
be static or actively driven. If used statically they must
be tied to VSS or VCC as appropriate. If actively driven,
they must be driven with CMOS levels (driven to VCC
or VSS).
Program Protect (PP)
The program protect input controls the hardware
program protect feature. When held LOW, hardware
program protection is disabled and the X24F064/032/
016 can be programmed normally. When this input is
held HIGH, and the PPEN bit in the program protect
register is set HIGH, program protection is enabled,
and nonvolatile writes are disabled to the selected
blocks as well as the program protect register itself.
PIN NAMES
Symbol
S0, S0, S1, S1, S2, S2
SDA
SCL
PP
VSS
VCC
NC
Description
Device Select Inputs
Serial Data
Serial Clock
Program Protect
Ground
Supply Voltage
No Connect
PIN CONFIGURATION
X24F016
8-Lead DIP & SOIC
S0 1
S1 2
S2 3
VSS 4
8 VCC
7 PP
6 SCL
5 SDA
14-Lead TSSOP
S0 1
S1 2
NC 3
NC 4
NC 5
S2 6
VSS 7
14 VCC
13 PP
12 NC
11 NC
10 NC
9 SCL
8 SDA
X24F032
8-Lead DIP & SOIC
S0 1
S1 2
S2 3
VSS 4
8 VCC
7 PP
6 SCL
5 SDA
14-Lead TSSOP
S0 1
S1 2
NC 3
NC 4
NC 5
S2 6
VSS 7
14 VCC
13 PP
12 NC
11 NC
10 NC
9 SCL
8 SDA
X24F064
8-Lead DIP & SOIC
NC 1
S1 2
S2 3
VSS 4
8 VCC
7 PP
6 SCL
5 SDA
20-Lead TSSOP
NC 1
NC 2
S1 3
NC 4
NC 5
NC 6
S2 7
NC 8
NC 9
NC 10
20 PP
19 VCC
18 PP
17 NC
16 NC
15 NC
14 SCL
13 SCL
12 NC
11 NC
Characteristics subject to change without notice. 2 of 17

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X24F064/032/016
DEVICE OPERATION
The X24F064/032/016 supports a bidirectional bus ori-
ented protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the
receiving device as the receiver. The device controlling
the transfer is a master and the device being controlled
is the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and
receive operations. Therefore, the X24F064/032/016
will be considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24F064/032/016 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition has
been met.
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
START Bit
STOP Bit
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
The X24F064/032/016 will respond with an acknowl-
edge after recognition of a start condition and its slave
address. If both the device and a write operation have
been selected, the X24F064/032/016 will respond with
an acknowledge after the receipt of each subsequent
eight-bit word.
In the read mode the X24F064/032/016 will transmit eight
bits of data, release the SDA line and monitor the line for
an acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24F064/
032/016 will continue to transmit data. If an acknowledge
is not detected, the device will terminate further data
transmissions. The master must then issue a stop condi-
tion to return the X24F064/032/016 to the standby power
mode and place the device into a known state.
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X24F064/032/016
Figure 3. Acknowledge Response From Receiver
SCL From
Master
1
Data Output
From Transmitter
89
Data Output
From Receiver
START
Acknowledge
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could
have up to eight X24F032/016’s on the bus or up to
four 24F064’s on the bus. The device addresses are
defined by the state of the S0, S1, and S2 inputs. Note
some of the slave addresses must be the inverse of the
corresponding input pin.
Figure 4. Slave Address
Device
Select
X24F064
High Order
Sector Address
S2 S1 A12 A11 A10 A9 A8 R/W
Device
Select
X24F032
High Order
Sector Address
S2 S1 S0 A11 A10 A9 A8 R/W
Device
Type
Identifier
X24F016
Device
Select
High Order
Sector Address
1 S2 S1 S0 A10 A9 A8 R/W
Also included in the slave address is an extension of the
array’s address which is concatenated with the eight bits
of address in the sector address field, providing direct
access to the entire SerialFlash Memory array.
The last bit of the slave address defines the operation to
be performed. When set HIGH a read operation is
selected, when set LOW a program operation is selected.
Following the start condition, the X24F064/032/016 moni-
tors the SDA bus comparing the slave address being
transmitted with its slave address device type identifier.
Upon a correct comparison of the device select inputs, the
X24F064/032/016 outputs an acknowledge on the SDA
line. Depending on the state of the R/W bit, the X24F064/
032/016 will execute a read or program operation.
PROGRAMMING OPERATIONS
The X24F064/032/016 offers a 32-byte sector program-
ming operation. For a program operation, the X24F064/
032/016 requires a second address field. This field con-
tains the address of the first byte in the sector. Upon
receipt of the address, comprised of eight bits, the
X24F064/032/016 responds with an acknowledge and
awaits the next eight bits of data, again responding with
an acknowledge. The master then transmits 31 more
bytes. After the receipt of each byte, the X24F064/032/
016 will respond with an acknowledge.
After the receipt of each byte, the five low order
address bits are internally incremented by one. The
high order bits of the sector address remain constant.
If the master should transmit more or less than
32 bytes prior to generating the stop condition, the
contents of the sector cannot be guaranteed. All inputs
are disabled until completion of the internal program
cycle. Refer to Figure 5 for the address, acknowledge
and data transfer sequence.
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X24F064/032/016
Figure 5. Sector Programming
Bus Activity:
Master
SDA Line
S
T
A
R
T
S
Bus Activity:
X24F016/032/064
Slave
Address
Sector
Address
AA
CC
KK
Data n
Data n + 1
AA
CC
KK
Data n + 31
S
T
O
P
P
A
C
K
Acknowledge Polling
The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to Flow 1.
Flow 1. ACK Polling Sequence
Program Operation
Completed
Enter ACK Polling
Issue
START
Issue Slave
Address and R/W = 0
ACK
Returned?
YES
Next
Operation
a Write?
YES
NO
NO
Issue Sector
Address
Issue STOP
Issue STOP
PROCEED
PROCEED
Characteristics subject to change without notice. 5 of 17