PPEN PP PEL Blocks Blocks
0 X 0 Locked Locked
0 X 1 Locked Programmable Programmable
1 LOW 0 Locked Locked
1 LOW 1 Locked Programmable Locked
X HIGH 0 Locked Locked
X HIGH 1 Locked Programmable Programmable
6685 PGM T05.2
The Program Protect (PP) pin and the nonvolatile
Program Protect Enable (PPEN) bit in the Status Reg-
ister control the programmable hardware write protect
feature. Hardware program protection is enabled when
PP pin is LOW, and the PPEN bit is “1”. Hardware
program protection is disabled when either the PP pin is
HIGH or the PPEN bit is “0”. When the chip is hardware
program protected, nonvolatile programming of the Sta-
tus Register in disabled, including the Block Lock bits
and the PPEN bit itself, as well as the Block Lock
sections in the memory array. Only the sections of the
memory array that are not Block Locked can be pro-
Note: Since the PPEN bit is program protected, it
cannot be changed back to a “0”, as long as
the PP pin is held LOW.
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
When reading from the SerialFlash memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25F064/032/016/008
device, followed by the 16-bit address. After the read
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO
line. The data stored in memory at the next address can
be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
When the highest address is reached the address
counter rolls over to address $0000, allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS HIGH. Refer to the Read
SerialFlash Memory Array Operation Sequence illustrated
in Figure 1.
To read the status register, the CS line is first pulled
LOW to select the device followed by the 8-bit instruc-
tion. After the read status register opcode is sent, the
contents of the status register are shifted out on the SO
line. The Read Status Register Sequence is illustrated
in Figure 2.
Prior to any attempt to program the X25F064/032/016/
008 device, the program enable latch must first be set by
issuing the PREN instruction (See Figure 3). CS is first
taken LOW, then the PREN instruction is clocked into
the X25F064/032/016/008 device. After all eight bits of
the instruction are transmitted, CS must then be taken
HIGH. If the user continues the programming operation
without taking CS HIGH after issuing the PREN instruc-
tion, the programming operation will be ignored.
To program the SerialFlash memory array, the user
issues the PROGRAM instruction, followed by the ad-
dress of the first location in the sector and then the data
to be programmed. The data is programmed in a 256-
clock operation. CS must go LOW and remain LOW for
the duration of the operation. The 32 bytes must reside
in the same sector and cannot cross sector boundaries.
If the address counter reaches the end of the sector
and the clock continues, or if fewer than 32 bytes are
clocked in, the contents of the sector cannot be guaranteed.
For the program operation to be completed, CS can only
be brought HIGH after bit 0 of data byte 32 is clocked in.
If it is brought HIGH at any other time the program
operation will not be completed. Refer to Figure 4 below
for a detailed illustration of the programming sequence
and time frames in which CS going HIGH is valid.
To program the status register, the PRSR instruction is
followed by the data to be programmed. Data bits 0, 1,
4, 5 and 6 must be “0”. This sequence is shown in Figure 5.
While the program cycle is in progress, following a
status register or memory write sequence, the status
register may be read to check the PIP bit. During this
time the PIP bit will be HIGH.
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is that the SCK input
must be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.