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X28C010
1M
X28C010
5 Volt, Byte Alterable E2PROM
128K x 8 Bit
FEATURES
Access Time: 120ns
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 50mA
—Standby: 500µA
Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
DESCRIPTION
The Xicor X28C010 is a 128K x 8 E2PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C010 also features DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28C010 supports Software Data
Protection option.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
PIN CONFIGURATIONS
CERDIP
FLAT PACK
SOIC (R)
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
X28C010
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3858 FHD F02.1
PGA
I/O0 I/O2 I/O3 I/O5 I/O6
15 17 19 21 22
A1 A0 I/O1 VSS I/O4 I/O7 CE
13 14 16 18 20 23 24
A2 A3
12 11
A10 OE
25 26
A4
10
A6
8
A5
9
A7
7
X28C010
(BOTTOM VIEW)
A11 A9
27 28
A8 A13
29 30
A12 A15 NC VCC NC NC A14
6 5 2 36 34 32 31
A16 NC NC WE NC
4 3 1 35 33
3858 FHD F20
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3858-3.1 4/3/97 T1/C0/D0 SH
1
PLCC
LCC
30
A7
A6
5 4 3 2 32 31 29
6 1 28
A14
A13
A5 7
27 A8
A4
A3
8 26
9
X28C010
(TOP VIEW)
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0
13
14
15 16 17 18 19 20
21
I/O7
EXTENDED LCC
30
4 3 2 32 31
1
A7 5
29 A14
A6 6
28 A13
A5 7
27 A8
A4
A3
8 26
9
X28C010
(TOP VIEW)
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0 13
21 I/O7
14 15 16 17 18 19 20
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSOP
3858 FHD F03.1
X28C010
40 OE
39 A10
38 CE
37 I/O7
36 I/O6
35 I/O5
34 I/O4
33 I/O3
32 NC
31 NC
30 VSS
29 NC
28 NC
27 I/O2
26 I/O1
25 I/O0
24 A0
23 A1
22 A2
21 A3
3858 ILL F21
Characteristics subject to change without notice

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X28C010
PIN DESCRIPTIONS
Addresses (A0–A16)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C010 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010.
FUNCTIONAL DIAGRAM
PIN NAMES
Symbol
A0–A16
I/O0–I/O7
WE
CE
OE
VCC
VSS
NC
A8–A16
X BUFFERS
LATCHES AND
DECODER
1M-BIT
E2PROM
ARRAY
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3858 PGM T01
A0–A7
Y BUFFERS
LATCHES AND
DECODER
CE
OE
WE
VCC
VSS
CONTROL
LOGIC AND
TIMING
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
3858 FHD F01
2

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X28C010
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE, which-
ever occurs last. Similarly, the data is latched internally by
the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows
two to two hundred fifty-six bytes of data to be consecu-
tively written to the X28C010 prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address), but
the page address (A8 through A16) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28C010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O DP TB 5 4 3 2 1 0
RESERVED
TOGGLE BIT
DATA POLLING
3858 FHD F11
DATA Polling (I/O7)
The X28C010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C010,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data. Note: If the
X28C010 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Toggle Bit (I/O6)
The X28C010 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3

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X28C010
DATA Polling I/O7
Figure 2. DATA Polling Bus Sequence
LAST
WE WRITE
CE
OE
VIH
I/O7
A0–A14
An
HIGH Z
VOL
An An
An
Figure 3. DATA Polling Software Flow
WRITE DATA
VOH
X28C010
READY
An An An
3858 FHD F12
DATA Polling can effectively halve the time for writing to
the X28C010. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implement-
ing the routine.
WRITES
COMPLETE?
NO
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
I/O7
COMPARE?
YES
NO
X28C010
READY
3858 FHD F13
4

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X28C010
The Toggle Bit I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WE WRITE
CE
OE
I/O6
VOH
*
VOL
* Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
HIGH Z
*
X28C010
READY
3858 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
COMPARE
OK?
YES
X28C010
READY
NO
3858 FHD F15
5