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PRELIMINARY
BYTE-WIDE
SMART 3 FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004S3, 28F008S3, 28F016S3
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
Smart 3 Flash: 2.7 V or 3.3 V VCC
and 2.7 V, 3.3 V or 12 V VPP
n High-Performance
120 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide Smart 3 FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide Smart 3 FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997
Order Number: 290598-004

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F004S3, 28F008S3, 28F016S3 may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION, 1997
*Third-party brands and names are the property of their respective owners.
CG-041493

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BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
CONTENTS
PAGE
1.0 INTRODUCTION .............................................5
1.1 New Features...............................................5
1.2 Product Overview.........................................5
1.3 Pinout and Pin Description ...........................6
2.0 PRINCIPLES OF OPERATION .....................11
2.1 Data Protection ..........................................12
3.0 BUS OPERATION .........................................12
3.1 Read ..........................................................12
3.2 Output Disable ...........................................12
3.3 Standby......................................................12
3.4 Deep Power-Down .....................................12
3.5 Read Identifier Codes Operation ................13
3.6 Write ..........................................................13
4.0 COMMAND DEFINITIONS ............................13
4.1 Read Array Command................................16
4.2 Read Identifier Codes Command ...............16
4.3 Read Status Register Command................16
4.4 Clear Status Register Command................16
4.5 Block Erase Command ..............................16
4.6 Program Command....................................17
4.7 Block Erase Suspend Command................17
4.8 Program Suspend Command .....................18
4.9 Set Block and Master Lock-Bit Commands 18
4.10 Clear Block Lock-Bits Command..............19
5.0 DESIGN CONSIDERATIONS ........................27
5.1 Three-Line Output Control..........................27
5.2 RY/BY# Hardware Detection ......................27
5.3 Power Supply Decoupling ..........................27
5.4 VPP Trace on Printed Circuit Boards...........27
5.5 VCC, VPP, RP# Transitions .........................27
5.6 Power-Up/Down Protection ........................27
5.7 VPP Program and Erase Voltages on Sub-
0.4µ S3 Memory Family ............................28
PAGE
6.0 ELECTRICAL SPECIFICATIONS..................29
6.1 Absolute Maximum Ratings........................29
6.2 Commercial Temperature Operating
Conditions .................................................29
6.3 Capacitance ...............................................29
6.4 DC Characteristics— Commercial
Temperature..............................................30
6.5 AC Characteristics—Read-Only
Operations—Commercial Temperature .....34
6.6 AC Characteristics—Write Operations—
Commercial Temperature..........................36
6.7 Block Erase, Program, and Lock-Bit
Configuration Performance—Commercial
Temperature..............................................38
6.8 Extended Temperature Operating
Conditions .................................................39
6.9 DC Characteristics—Extended
Temperature..............................................39
6.10 AC Characteristics—Read-Only
Operations—Extended Temperature .........39
7.0 ORDERING INFORMATION..........................40
8.0 ADDITIONAL INFORMATION .......................40
PRELIMINARY
3

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BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
E
Number
-001
-002
-003
-004
REVISION HISTORY
Description
Original version
Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program.
Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead
PSOP to TB = Ext. Temp. 44-Lead PSOP
Updated Ordering Information and table
Correction to table, Section 6.2.3. Under ILO Test Conditions, previously read VIN = VCC
or GND, corrected to VOUT = VCC or GND
Section 6.2.7, modified Program and Block Erase Suspend Latency Times
Updated disclaimer
Added 2.7 V VPP specifications.
Added µBGA* CSP pinouts and corrected error in PSOP pinout
Added Design Consideration for VPP Program and Erase Voltages on future sub-0.4µ
devices.
4 PRELIMINARY

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BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
1.0 INTRODUCTION
This datasheet contains 4-, 8-, and 16-Mbit Smart 3
FlashFile memory specifications. Section 1.0
provides a flash memory overview. Sections 2.0,
3.0, 4.0, and 5.0 describe the memory organization
and functionality. Section 6.0 covers electrical
specifications for commercial and extended
temperature product offerings. Ordering information
is provided in Section 7.0. Finally, the byte-wide
Smart 3 FlashFile memory family documentation
also includes application notes and design tools
which are referenced in Section 8.0.
1.1 New Features
The byte-wide Smart 3 FlashFile memory family
maintains backwards-compatibility with Intel’s
28F008SA-L. Key enhancements include:
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
They share a compatible status register, software
commands, and pinouts. These similarities enable
a clean upgrade from the 28F008SA-L to byte-wide
Smart 3 FlashFile products. When upgrading, it is
important to note the following differences:
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
VPPLK has been lowered from 6.5 V to 1.5 V to
support low VPP voltages during block erase,
program, and lock-bit configuration operations.
Designs that switch VPP off during read
operations should transition VPP to GND.
To take advantage of SmartVoltage tech-
nology, allow VPP connection to 3.3 V.
For more details see application note AP-625,
28F008SC Compatibility with 28F008SA (order
number 292180).
1.2 Product Overview
The byte-wide Smart 3 FlashFile memory family
provides density upgrades with pinout compatibility
for the 4-, 8-, and 16-Mbit densities. The 28F004S3,
28F008S3, and 28F016S3 are high-performance
memories arranged as 512 Kbyte, 1 Mbyte, and
2 Mbyte of eight bits. This data is grouped in eight,
sixteen, and thirty-two 64-Kbyte blocks which are
individually erasable, lockable, and unlockable in-
system. Figure 5 illustrates the memory
organization.
SmartVoltage technology enables fast factory
programming and low power designs. Specifically
designed for 3 V systems, Smart 3 FlashFile
components support read operations at 2.7 V and
3.3 V VCC and block erase and program operations
at 2.7 V, 3.3 V and 12 V VPP. The 12 V VPP option
renders the fastest program performance which will
increase your factory throughput. With the 2.7 V or
3.3 V VPP option, VCC and VPP can be tied together
for a simple, low-power 2.7 V or 3 V design. In
addition to the voltage flexibility, the dedicated VPP
pin gives complete data protection when VPP
VPPLK.
Internal VPP detection circuitry automatically
configures the device for optimized block erase and
program operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within 1.1 second
(12 V VPP), independent of other blocks. Each block
can be independently erased 100,000 times
(1.6 million block erases per device). A block erase
suspend operation allows system software to
suspend block erase to read data from or program
data to any other block.
Data is programmed in byte increments typically
within 7.6 µs (12 V VPP). A program suspend
operation permits system software to read data or
execute code from any other flash memory array
location.
PRELIMINARY
5