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FUJITSU SEMICONDUCTOR
DATA SHEET
32-bit Microcontroller
CMOS
FR60 MB91313 Series
DS07-16706-1E
MB91F313
DESCRIPTION
The FR family* is a line of microcontrollers based on a high-performance 32-bit RISC CPU that contains a variety
of built-in I/O resources for embedded control applications which require high-performance, high-speed CPU
processing.
MB91313 series has multiple communication macro channels, suitable for embedded control applications such
as TV control.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
FEATURES
1. FR CPU
• 32-bit RISC load/store architecture with a five-stage pipeline
• Operating frequency 33 MHz (oscillator frequency: 16.5 MHz; oscillator frequency multiplier: 2 (PLL clock
multiplication method))
• 16-bit fixed length instructions (basic instructions)
• Instruction execution speed : 1 instruction per cycle
• Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions :
Instructions suitable for embedded applications
• Function entry/exit instructions and register data multi-load store instructions :
Instructions supporting C language
• Register interlock functions : Facilitates assembly-language coding
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved

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MB91313 Series
• On-chip multiplier supported at the instruction level
- Signed 32-bit multiplication : 5 cycles
- Signed 16-bit multiplication : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture enabling program access and data access to be executed simultaneously
• Instruction prefetch feature implemented using a 4-word queue in the CPU
• Instruction compatible with the FR family
2. Simple External Bus Interface
• Function as an 8-bit or 16-bit multiplexed bus through programmatic settings
• Operating frequency : Max 16.5 MHz
• Multiplexed I/O for 8/16-bit data/address
• Capable of chip-select signal output for 4 completely independent areas configurable in minimum units of
64 Kbytes
• Basic bus cycle : 3 cycles
• Automatic wait cycle generation function to be programmed for each area
• Unused data/address/control signal pins can serve as general-purpose I/O
3. Built-in Memory
Flash : 544 Kbytes, RAM : 32 Kbytes
4. DMAC (DMA Controller)
• 5 channels
• Two transfer sources : Internal peripheral/software
• Addressing modes : 20/24-bit address selectable (increment/decrement/fixed)
• Transfer modes : Burst transfer/step transfer/block transfer
• Transfer data size : Selectable from 8, 16, or 32 bits
5. Bit Search Module (for REALOS)
Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a
word
6. 16-bit Reload Timer (Including 1 Channel for REALOS)
• 6 channels
• Internal clock: Frequency division selectable from 2, 8, and 32
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MB91313 Series
7. Serial Interface
• 11 channels
• Full duplex double buffer
• Communication mode : Asynchronous (start-stop synchronization) communication, clock synchronous
communication (8.25 Mbps Max), I2C* standard mode (100 kbps Max), high-speed mode (400 kbps Max)
• Parity on/off selectable
• Baud rate generators for each channel
• Extensive error detection functions : Parity, frame, and overrun
• External clock can be used as transfer clock
• Ch.0 to ch.2 : DMA transfers/each equipped with a pair of 16-byte transmit and receive FIFOs
• Ch.8 to ch.10 : 5 V tolerant
• Ch.8 : Open drain outputs
• I2C bridge function (bridges between channels 0, 1, and 2)
• SPI mode
8. Interrupt Controller
• External interrupt lines: Total of 24 lines (INT23 to INT0)
• Interrupts from internal peripherals
• Programmable 16 priority levels
• Capable of using wakeup from STOP mode
9. 10-bit A/D Converter
• 10 channels
• Successive approximation type : Conversion time : About 7.94 µs
• Conversion mode : Single-shot conversion mode, scan conversion mode
• Activation sources : Software/external trigger
10. PPG
• 4 channels
• 16-bit down counter, 16-bit data register with cycle setting buffer
• Internal clock : Frequency division selected from 1, 4, 16, and 64
• Support for automatic cycle setting by DMA transfer
• Function for supporting remote control transmission
• Open drain outputs
11. PWC
• 1 channel (1 input)
• 16-bit up counter
• Simple digital lowpass filter
12. Multi-function Timer
• 4 channels
• Lowpass filter eliminating noise below a pre-set clock frequency
• Capable of pulse width measurement using seven types of clock signals
• Pin input event count function
• Interval timer function using seven types of clock signals and external input clock
• Internal HSYNC counter mode
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MB91313 Series
(Continued)
13. HDMI-CEC/Remote Control Receiver
• 2 channels
• HDMI-CEC receiver function (with automatic ACK response function)
• Remote control receiver function (built-in 4-byte receive buffer)
14. Other Interval Timers
• Watch timer (32 kHz, counts up to a maximum of 60 seconds)
• Watchdog timer
15. I/O Ports
Max 86 ports
16. Other Features
• Internal oscillator circuit as a clock source
• INITX provided as a reset pin
• Watchdog timer reset and software reset are available
• Stop and sleep modes supported as low-power consumption modes
• Gear function
Time-base timer
5 V tolerant I/O (some pins)
• Package LQFP-120, 0.50 mm pitch, 16.0 mm × 16.0 mm
• CMOS technology (0.18µm)
• Power supply voltage 3.3 V ± 0.3 V, 1.8 V ± 0.15 V dual power supply
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these compo-
nents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
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PIN ASSIGNMENT
MB91313 Series
(TOP VIEW)
VSS 1
VDDI 2
P23/SIN1 3
P24/SOT1/SDA1 (I2C bridge) 4
P25/SCK1/SCL1 (I2C bridge) 5
P26/SIN2 6
P27/SOT2/SDA2 (I2C bridge) 7
P30/SCK2/SCL2 (I2C bridge) 8
P31/TOT0 9
P32/TOT1 10
P33/TOT2 11
P34/TIN0 12
P35/TIN1 13
P36/TIN2 14
P37/RIN 15
P40/TMO0/INT16 16
P41/TMO1/INT17 17
P42/TMO2/INT18 18
P43/TMO3/INT19 19
P44/TMI0/INT20 20
P45/TMI1/INT21/SIN10 21
P46/TMI2/INT22/SOT10/SDA10 22
P47/TMI3/INT23/SCK10/SCL10 23
P60/TOT3/TRG2 24
P61/TOT4/TRG3 25
P62/TOT5/RDY 26
P63/TIN3/CLK 27
P64/TIN4 28
P65/TIN5 29
VDDE 30
90 VDDE
89 IBREAK
88 ICLK
87 ICS2
86 ICS1
85 ICS0
84 ICD3
83 ICD2
82 ICD1
81 ICD0
80 TRSTX
79 PC7/TRG1
78 PC6/TRG0
77 PC5/PPGB
76 PC4/PPGA
75 PC3
74 PC2/SCK9/SCL9
73 PC1/SOT9/SDA9
72 PC0/SIN9
71 PE7/SCK8/SCL8/INT7
70 PE6/SOT8/SDA8/INT6
69 PE5/SIN8/INT5
68 PE4/PPG3/INT4
67 MD2
66 MD1
65 MD0
64 VDDI
63 X0
62 X1
61 VSS
(FPT-120P-M21)
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