IID4.pdf 데이터시트 (총 2 페이지) - 파일 다운로드 IID4 데이타시트 다운로드

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Description
IIDx is a family of non-inverting clock drivers with a single output.
Logic Symbol
Truth Table
IIDx
AQ
AQ
AQ
LL
HH
HDL Syntax
Verilog .................... IIDx inst_name (Q, A);
VHDL...................... inst_name: IIDx port map (Q, A);
Pin Loading
Pin Name
A
IID1
1.0
Equivalent Loads
IID2 IID3 IID4
1.0 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
IID1 1.0
IID2 2.0
TBD
TBD
2.3
3.8
IID3 3.0
TBD
5.5
IID4 3.0
IID6 4.0
TBD
TBD
7.6
11.0
a. See page 2-15 for power equation.
IID6
2.1
3-124
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Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Number of Equivalent Loads
IID1 From: A
To: Q
tPLH
tPHL
Number of Equivalent Loads
1
0.21
0.21
1
4
0.31
0.32
8
IID2 From: A
To: Q
tPLH
tPHL
0.15
0.23
0.27
0.35
Number of Equivalent Loads
1
11
IID3 From: A
To: Q
tPLH
tPHL
0.15
0.18
0.28
0.31
Number of Equivalent Loads
1
14
IID4 From: A
To: Q
tPLH
tPHL
0.20
0.21
0.29
0.34
Number of Equivalent Loads
1
21
IID6 From: A
To: Q
tPLH
tPHL
0.22
0.25
0.34
0.37
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
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8
0.42
0.44
15
0.38
0.45
22
0.38
0.41
28
0.39
0.44
42
0.44
0.47
13
0.56
0.59
22
0.49
0.56
32
0.47
0.50
42
0.48
0.54
62
0.52
0.58
17 (max)
0.68
0.72
30 (max)
0.60
0.69
43 (max)
0.57
0.61
56 (max)
0.57
0.65
83 (max)
0.60
0.69
3-125