OR42.pdf 데이터시트 (총 2 페이지) - 파일 다운로드 OR42 데이타시트 다운로드

No Preview Available !

25[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
OR4x is a family of 4-input gate which performs the logical OR function.
Logic Symbol
Truth Table
OR4x
A
B
C
Q
D
A
B
C
Q
D
A B CDQ
LLLLL
HXXXH
XHXXH
XXHXH
XXXHH
HDL Syntax
Verilog .................... OR4x inst_name (Q, A, B, C, D);
VHDL...................... inst_name: OR4x port map (Q, A, B, C, D);
Pin Loading
Pin Name
A
B
C
D
OR41
1.0
1.0
1.0
1.0
Equivalent Loads
OR42
OR44
1.0 3.2
1.0 3.2
1.0 3.2
1.0 3.2
OR46
3.1
3.1
3.1
3.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
OR41
3.0
TBD
4.8
OR42
4.0
TBD
7.8
OR44
8.0
TBD
12.3
OR46
9.0
TBD
16.8
a. See page 2-15 for power equation.
3-215

No Preview Available !

25[
$0,+*  PLFURQ &026 *DWH $UUD\
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
OR41
Number of Equivalent Loads
From: Any Input
To: Q
tPLH
tPHL
Number of Equivalent Loads
1
0.22
0.31
1
4
0.31
0.46
8
OR42
From: Any Input
To: Q
tPLH
tPHL
0.25
0.35
0.36
0.55
Number of Equivalent Loads
1
14
OR44
From: Any Input
To: Q
tPLH
tPHL
0.19
0.38
0.30
0.59
Number of Equivalent Loads
1
21
OR46
From: Any Input
To: Q
tPLH
tPHL
0.22
0.50
0.33
0.69
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
8
0.43
0.66
15
0.45
0.72
28
0.41
0.74
42
0.44
0.83
®
13
0.58
0.91
22
0.55
0.88
42
0.50
0.86
62
0.55
0.94
17 (max)
0.69
1.10
30 (max)
0.66
1.05
56 (max)
0.59
0.97
83 (max)
0.67
1.05
3-216