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Description
ODCSXExx is a family of 4 to 16 mA, non-inverting, CMOS-level, tristate output buffer pieces with active low enables
and controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSXExx
EN
SL
A
PADM
EN A PADM
LL
L
LH
H
HX
Z
HDL Syntax
Verilog .................... ODCSXExx inst_name (PADM, A, EN);
VHDL...................... inst_name: ODCSXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load)
EN (eq-load)
PADM (pF)
ODCSXE04
2.3
6.9
4.94
Power Characteristics
Cell Output Drive (mA)
ODCSXE04
4
ODCSXE08
8
ODCSXE12
12
ODCSXE16
16
a. See page 2-15 for power equation.
ODCSXE08
2.3
6.9
4.94
Load
ODCSXE12
2.3
6.9
4.94
ODCSXE16
2.3
6.9
4.94
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
218.9
TBD
240.3
TBD
261.1
TBD
283.9
4-17

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Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODCSXE04
From: A
tPLH
To: PADM tPHL
3.23
3.03
From: EN
tZH
To: PADM tZL
2.93
2.88
Capacitive Load (pF)
15
ODCSXE08
From: A
tPLH
To: PADM tPHL
2.33
2.17
From: EN
tZH
To: PADM tZL
2.24
1.92
Capacitive Load (pF)
15
ODCSXE12
From: A
tPLH
To: PADM tPHL
2.12
1.87
From: EN
tZH
To: PADM tZL
1.82
1.68
Capacitive Load (pF)
15
ODCSXE16
From: A
tPLH
To: PADM tPHL
1.67
2.03
From: EN
tZH
To: PADM tZL
1.38
1.74
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
Tristate Timing
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To
EN PADM
Parameter
tHZ
tLZ
ODCSXE04
0.82
0.86
50
6.83
6.71
100
12.02
12.06
200
22.08
22.73
6.57
11.74
21.76
6.64
11.91
22.47
50
4.22
4.05
100 200
6.89 12.17
6.75 12.18
4.17 6.85 12.13
3.84 6.54 11.96
50 100 200
3.37 5.20 8.84
3.14 4.97 8.54
3.11 4.89 8.45
2.96 4.74 8.28
50 100 200
2.25 3.03 4.47
2.88 4.09 6.67
1.94 2.70 4.14
2.60 3.86 6.46
Cell
ODCSXE08
ODCSXE12
1.04 1.27
1.04 1.20
300 (max)
31.52
33.29
31.25
33.18
300 (max)
17.43
17.62
17.34
17.41
300 (max)
12.37
12.03
12.08
11.85
300 (max)
5.84
9.37
5.54
9.13
ODCSXE16
1.53
1.38
4-18