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Description
ODCXIPxx is a family of 1 to 8 mA, inverting, CMOS-level, output buffer pieces with P-channel, open-drains (pull-up).
Logic Symbol
Truth Table
ODCXIPxx
A
PADM
A PADM
LH
HZ
Z = High Impedance
HDL Syntax
Verilog .................... ODCXIPxx inst_name (PADM, A);
VHDL...................... inst_name: ODCXIPxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
PADM (pF)
ODCXIP01
2.8
4.92
Load
ODCXIP02
ODCXIP04
2.8 2.8
4.92 4.92
ODCXIP08
3.9
4.93
Power Characteristics
Cell Output Drive (mA)
ODCXIP01
1
ODCXIP02
2
ODCXIP04
4
ODCXIP08
8
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
TBD
148.8
TBD
153.6
TBD
162.0
TBD
178.9
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Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
ODCXIP01
Capacitive Load (pF)
From: A
To: PADM
tZH
15
4.73
ODCXIP02
Capacitive Load (pF)
From: A
To: PADM
tZH
15
2.54
ODCXIP04
Capacitive Load (pF)
From: A
To: PADM
tZH
15
1.75
ODCXIP08
Capacitive Load (pF)
From: A
To: PADM
tZH
15
1.33
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
25
6.87
50
6.19
50
3.62
50
2.26
35
8.98
75
8.78
100
6.26
100
3.59
50
12.13
100
11.38
200
11.57
200
6.24
Tristate Timing
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To
Parameter
ODCXIP01
Cell
ODCXIP02 ODCXIP04
APADM
tHZ 1.04 0.89 1.05
ODCXIP08
1.38
®
75 (max)
17.31
150 (max)
16.61
300 (max)
16.92
300 (max)
8.91
4-22