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Description
ODCXXXxx is a family of 1 to 24 mA, non-inverting, CMOS-level output buffer pieces.
Logic Symbol
Truth Table
ODCXXXxx
A
PADM
A PADM
LL
HH
HDL Syntax
Verilog .................... ODCXXXxx inst_name (PADM, A);
VHDL...................... inst_name: ODCXXXxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
ODCXXX01
4.3
ODCXXX02
4.3
ODCXXX04
6.2
Load
ODCXXX08
8.3
ODCXXX12
8.2
Power Characteristics
Cell Output Drive (mA)
ODCXXX01
1
ODCXXX02
2
ODCXXX04
4
ODCXXX08
8
ODCXXX12
12
ODCXXX16
16
ODCXXX24
24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
149.5
TBD
155.0
TBD
165.6
TBD
189.8
TBD
210.7
TBD
234.8
TBD
248.2
ODCXXX16
8.2
ODCXXX24
10.3
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Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODCXXX01
From: A
tPLH
To: PADM tPHL
4.55
4.71
Capacitive Load (pF)
15
ODCXXX02
From: A
tPLH
To: PADM tPHL
2.46
2.77
Capacitive Load (pF)
15
ODCXXX04
From: A
tPLH
To: PADM tPHL
1.45
1.52
Capacitive Load (pF)
15
ODCXXX08
From: A
tPLH
To: PADM tPHL
1.17
1.22
Capacitive Load (pF)
15
ODCXXX12
From: A
tPLH
To PADM tPHL
1.15
1.20
Capacitive Load (pF)
15
ODCXXX16
From: A
tPLH
To: PADM tPHL
1.29
1.33
Capacitive Load (pF)
15
ODCXXX24
From: A
tPLH
To: PADM tPHL
1.27
1.09
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
25
6.53
6.90
50
6.13
6.39
50
3.31
3.43
50
2.11
2.12
50
1.85
1.86
50
1.83
1.85
50
1.80
1.51
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35
8.68
9.09
50
11.93
12.37
75 (max)
17.07
17.81
75 100 150 (max)
8.76
11.37
16.53
9.02
11.68
17.05
100
5.97
6.09
200
11.30
11.35
300 (max)
16.62
16.64
100
3.45
3.41
200 300 (max)
6.11 8.76
6.00 8.61
100
2.80
2.74
200 300 (max)
4.61 6.36
4.47 6.19
100
2.54
2.56
200 300 (max)
3.91 5.24
3.90 5.15
100
2.51
2.02
200 300 (max)
3.87 5.17
2.94 3.81
4-27