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Description
ODTHXX24 is a high performance,24 mA, non-inverting, TTL-level output buffer piece.
Logic Symbol
Truth Table
Pin Loading
ODTHXX24
A
PADM
A PADM
LL
HH
Load
A 14.5 eql
HDL Syntax
Verilog .................... ODTHXX24 inst_name (PADM, A);
VHDL...................... inst_name: ODTHXX24 port map (PADM, A);
Power Characteristics
Parameter
Static IDD (TJ = 85°C)
EQLpd
See page 2-15 for power equation.
Value
TBD
249.7
Units
nA
Eq-load
Output Propagation Delays
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To Parameter
15
A
PADM
tPLH
tPHL
0.54
0.84
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
0.81
1.30
Capacitive Load (pF)
100
1.16
1.95
200
1.84
3.25
300 (max)
2.57
4.56
4-37